In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The On Product Overlay (OPO) budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer to wafer (W2W) variations. To save product area and reduce scribe line width, small alignment mark is evaluated to achieve the similar results as reference mark and to optimize the OPO performance. In this work, we will show the experimental results of small alignment mark and investigate the on product overlay performance by simulation.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The on-product overlay budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer-to-wafer variation. Due to the complexity, a holistic methodology is used to combine various alignment solutions to achieve the optimal on-product overlay performance. In this paper, we evaluated the holistic method by simulation and experiment for DUV layers. We illustrate the expected on-product overlay improvement.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.