In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
The market transition from 2D to 3D-NAND in recent years requires strict focus control and monitoring solutions. ASML’s μDBF targets (micro Diffraction Based Focus) enable on-product focus measurement which can be used to optimize scanner correction. Additionally, dense computational focus maps can be generated by combining μDBF measurements with scanner metrology such as non-correctable leveling error. This paper discusses the focus variability observed on memory layers through on product focus monitoring. This work will show how exposure at best focus can be performed for immersion lithography in the case of strong focus fingerprints. Focus monitoring data from μDBF and computational focus metrology will be used to generate and apply corrections on two 3D-NAND layers.
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