Computational Lithography (CL) has proven to be an enabling technology, not only in Optical Proximity Correction and Verification, but in the specification of design rules and the development of new Resolution Enhancement Techniques (RET). This course will cover a broad spectrum of the field of CL; from the need for simulation, to its use in RET development and Design for Manufacturability (DfM), to recent advances in modeling techniques. The course material assumes a basic understanding of lithography processes and methods to characterize those processes, and will focus primarily on applications of CL. RET development will be discussed with an emphasis on double patterning. Future challenges in predictive modeling, along with the special challenges of modeling for DfM applications, will also be presented.

This course provides the attendee with sufficient technical background on Resolution Enhancement Techniques (RET) in optical lithography and Design for Manufacturability (DfM) in VLSI production to be able to appreciate key challenges and opportunities in these rapidly emerging technologies. The course explains fundamental physical principles governing optical lithography in VLSI manufacturing, leading to a solid understanding of RET and their impact on integrated circuit design. Through practical examples and theoretical discussion, the instructors will provide insight into the evolution of DfM and will contrast different DfM approaches for leading edge technology nodes. This course will primarily enable you to put key aspects of the rapidly emerging field of DfM into a solid technical framework to fully appreciate their impact on the IC business. The instructors have been teaching a very popular course on resolution enhancement techniques in optical lithography for the past five years and have now decided to adjust the focus of the course to keep up with industry trends.

Design for Manufacturability (DfM) means different things to different people: those on the design side of our business see it as the art of reducing dimensional and parametric conservatism while protecting aggressive time to market targets, those on the manufacturing side look to DfM to preserve profitability in light of increasing process complexity. Regardless of individual motivations, it is clear that DfM will continue to gain importance as traditional CMOS scaling is rapidly coming to an end. This short course will review the most popular manufacturability analysis techniques and their uses in DfM-enhanced design flows. Model-based techniques such as critical area analysis, lithography hotspot detection, and CMP thickness prediction will be contrasted to rules based techniques such as recommended design rules or enhanced routing rules. Differences between feed-back techniques such as process aware layout optimization and feed-forward techniques such as restricted design rules and design aware manufacturing will be discussed. The advantages and challenges of introducing manufacturability knowledge early in the design flow will be compared to those of applying manufacturability considerations late. Finally, the most prominent opportunities for innovation in DfM for technology nodes beyond 65nm will be reviewed.

As the microelectronic industry’s need for dimensional scaling continues to outpace the availability of patterning systems with sufficient resolving power, resolution enhancement techniques (RET) of ever increasing complexity are becoming commonplace. The most severely resolution challenged products competing at the leading edge of the technology roadmap, are relying on lithography friendly designs as a key component of their design for manufacturability (DfM) strategy. This course will explain lithography resolution limits, basic concepts of RET and their layout impact, and optimization techniques for high resolution lithography. The increasing importance of lithography friendly design, however, does not alleviate the need for other DfM techniques addressing random and systematic failure mechanism such as critical area analysis (CAA), layout redundancy, or chemical mechanical polishing (CMP) aware layout optimization. This course will review a variety of process characterization techniques and their uses in DfM. Combining distinctly different DfM techniques into a cohesive optimization solution and then integrating this solution into existing design flows presents its own set of challenges. By reviewing the basic elements of common design flows and exploring how emerging and established DfM solutions affect such flows, this course will convey a broad system level view of an integrated DfM approach.