The practicability and methodology of applying resolution-enhancement-technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from -4.2 to -15.8% with the four fabrication-friendly layout approaches. The area change of five test circuits using the four approaches range from -16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results.
The grid placement of contacts and gates enables more effective
use of resolution enhancement techniques, which in turn allow a
reduction of critical dimensions. Although the regular placement
adds restrictions during cell layout, the overall circuit area can
be made smaller and the extra manufacturing cost can be kept to
the lowest by a careful selection of the grid pitch, using
template-trim lithography method, allowing random contact
placement in the vertical direction, and using rectangular rather
than square contacts. The purpose of this work is to optimize the
gridded-layout-based process. The trade-off between the layout
area and manufacturing cost, and the determination of the minimum
grid pitch are discussed in this paper. We demonstrate that it is
a 1-D scaling instead of the conventional 2-D scaling for standard
cells and the narrow MOSFETs inside after the application of the
gridded layout on the contact and gate levels. The corresponding
effects on circuit performances, including the leakage current,
are also explored.
The layout strategies of standard cells with regularly-placed
contacts and gates are studied. The regular placement enables more
effective use of resolution enhancement technologies, which in
turn allows a reduction of critical dimensions. Although regular
placement of contacts and gates adds restrictions during cell
layout, the overall circuit area can be made smaller and the
number of extra masks and exposures can be kept to the lowest by
careful selection of the grid pitch, using template-trim
lithography method, allowing random contact placement in the
vertical direction, and using rectangular rather than square
contacts. Three different fabrication-friendly layouts are
compared in this study. The average area change of 64 standard
cells in a 130nm library range from -4.2% to -1.2% with
the 3 fabrication-friendly layout approaches. The area change of 5
test circuits using the 3 approaches range from -5.4% to
+2.6%. Power consumption and intrinsic delay also improve with
the decrease in circuits area, which is verified with the
examination results.
The impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is studied. Although snapping contacts to grid adds restrictions during layout design, smaller circuit area can be achieved by careful selection of the grid pitch, raising the lower limit of transistor width, applying double exposure, and shrinking the minimum contact pitch enabled by more effective application of resolution enhancement technologies. The technique is demonstrated on the contact level of 250-nm standard cells with the minimum contact pitch shrunk by 10%. The area change of 84 cells ranges from -20% to 25% with a median decrease of 5%. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2% respectively. Delay and power consumption are also estimated to decrease with area.
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