Sub-Resolution Assist Features (SRAF) are a widely used Resolution Enhancement Technique (RET) used in
Optical Lithography. They are used to enhance the printability of the main features. Model Based SRAF (MBSRAF)
are now the state of art method for placing SRAF, where numerical simulation is used to predict the optimal
SRAF size and location. When a slight change in the environment occurs, very small numerical differences may
result, and in some cases for very complex structures, the numerical technique may drive to a different solution,
resulting in SRAF solution inconsistency. In addition following the initial placement by MB-SRAF, SRAF Print
Avoidance (SPA) models are utilized to modify the SRAF size and placement, to prevent the SRAF printing. This
step may change the SRAF solution and consequently cause inconsistency. In this work, a case of SRAF
inconsistency is shown and an alternative solution will be presented.
A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will
outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm
technology node. They consist mainly of the introduction of a new software for optical proximity correction, the
introduction of model based process window correction, the switch to model based etch proximity correction, and
support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.
The design challenges associated with alternating phase shifted mask lithography are discussed, solutions which had
been developed to address these challenges are reviewed, and parallels to current design for manufacturability
implementation issues are identified. Leveraging these insights, the positive attributes of a well integrated design for
manufacturability enhanced design flow are proposed. Specific topics covered in the paper are: the need to complement
error-detection with streamlined layout-correction, the risk of providing too much unstable information too early in the
design optimization flow, the efficiencies of prescriptive 'correct-by-construction' solutions, and the need for seamless
integration into existing design flows. For the benefit of the non-lithographer, the discussion of these detailed topics is
preceded by a brief review of alternating phase shifted mask lithography principles and benefits.
In the course of using Optical Proximity Correction (OPC) to optimize contact printing, the obvious solution is not
always the correct solution. This paper will explore two different types of contact layers, with two different sets of
objectives. In the first type of contact layer, the primary objective is to achieve consistent area uniformity. For these
designs, use of contacts without serifs over contacts with traditional corner serifs will result in a mask that has a lower
data volume input to the mask writer and an easier time in inspection and repair. We also show that on the wafer, this
simpler style of OPC will result in lower variation of area and CD. In second type of contact layer, there are additional
complicating factors over the first type of contact layer in that these mask designs include layouts with different sizes of
contacts that must be printed simultaneously. As contacts get pushed close together on corner to corner type spacing,
traditional serifs will be more likely to drive mask inspection issues and high mask error enhancement factor (meef). One
way to address this is with OPC that employs inverse serifs, with the center fragment of the rectangle pushed out and the
corners pushed in. This approach reduces meef and provides better image parameters for lower variability through
process window. However, this solution does not lend itself to very aggressive correction to achieve aggressive contact
aspect ratios. We compare these different OPC strategies (squares, traditional corner serifs and inverse corner serifs) and
describe the strengths and weaknesses of each approach.
Optical Proximity Correction (OPC) relies on predictive modeling to achieve consistent wafer results. To that end,
understanding all sources of variation is essential to the successful implementation of OPC. This paper focuses on
challenging SRAM layouts of contacts to study the sources of wafer variation. A range of shape geometries and contact
configurations are studied. Contact shapes are no longer restricted to simple rectangles on the mask, some more complex
OPC outputs may include shapes like H's or T's or even more fragmented figures. The result is a large group of
parameters that can be measured at both mask and wafer level. The dependence of mask variation on geometry is studied
through the statistical distributions of parameter variations. The mask metrology output is expanded from traditional
linear dimensional measurements to include area, line edge roughness, corner rounding, and shape-to-shape metrics.
Wafer mask error enhancement factor (MEEF) is then calculated for the various contact geometries. This collection of
data makes it possible to study variation on many levels and determine the underlying source of wafer variations so that,
ultimately, they can be minimized.
The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.
With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications.
This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.
As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM’s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.
The rapidly escalating complexity of resolution enhancement techniques (RET), now commonplace in leading edge lithography, requires accurate verification to avoid yield and performance problems on the patterned wafers. Model-based verification techniques that have been derived from optical proximity correction (OPC) obtain the required checking speed from sparse sampling of the layout at discrete evaluation points along the edges of layout patterns. This sparse sampling allows accurately calibrated models to be used for full chip checking applications. However, there is a demonstrated risk of missing significant patterning errors due to the sparse and edge-centric sampling of the layout. Grid-based simulation approaches which calculate the image on a fine grid over the entire layout space accurately detect patterning problems anywhere in the layout, but can be executed at reasonable runtimes for aerial image models only. The challenge for full-chip model-based verification of RET-enhanced layouts is, therefore, a trade-off between sparse, edge-centric simulation using accurate models versus simulations using approximate models over the entire layout space. This paper presents an approach, termed contourIFV, that has been demonstrated to overcome the aforementioned problems and has been shown to provide significant value in the verification of the RET and OPC prescription.
Optical Proximity Correction has emerged as an industry standard technique to reproduce the desired shapes on wafers as pattern dimensions are approaching the optical resolution limits. However secondary effects, if not properly controlled, may impede successful application of this technique. In order to better assess these factors we have divided the overall pattern formation process into several obvious components: The illumination system, mask, projection optics, resist system and finally etch processes. Each one of these components influences the optical proximity effects observed in the final pattern. The dependence of optical proximity corrections on the type of illumination is fairly well known and will only be touched on. Variations in the mask manufacturing process such as deviations of the mask critical dimension from its nominal value will be discussed. The type of e-beam exposure tool used to write the mask was found to have profound impact on optical proximity correction and therefore specifying the type of mask writing tool and sometimes even its writing mode to ensure reproducible results is required. Lens aberrations in the optical exposure tool and their impact were studied using aerial image simulations. Examples of optical proximity curves from different first generation tools show significant differences even between tools of the same type. Resist effects and the variations induced by modifying etch processes were investigated emphasizing that a fairly detailed control of the overall pattern formation process is necessary to successfully implement any OPC approach.
Many semiconductor chip designs require precise simultaneous control of both the width and length of asymmetric features. Line shortening due to optical, resist processing, and mask effects cause the process windows for width and length to diverge. Typically differential mask biasing has ben used to maximize the common process window for both axes. As we enter the gigabit era limitations in grid size and mask write times may become significant restrictions to meeting required device tolerances with that approach. Simulations of aerial image and resist processing using SPLAT and LEOPOLD indicate that for a given mask there is considerable latitude to adjust the length of features without a significant loss of process window. An experimental design matrix was used to verify the simulation results and develop a regression mode of pupil fill, numerical aperture, and resist diffusion effects. This model was then applied to optimize the processing conditions for several product masks. This technique is particularly useful early in the development cycle when mask to mask repeatability is poor and lead times are long. It may also be use to fine tune image sizes in manufacturing.
The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.
In pattern transfer, as in any other method of information transfer, the output is usually a nonlinear function of the input. Lithography at the limit of resolution is an excellent object to demonstrate this. Printing structures smaller than 300 nm with a 4 X 0.5NA tool, the derivative of the pattern transfer function, or the ratio of pattern size variations on the wafer over pattern size variations at the mask level, is not a 4:1, as one would expect from the demagnification of the step and scan tool. In other words, below 300 nm, mask linewidth variations (for example butting errors of the mask writing tool) print at about twice their expected size. In the concept of the pattern transfer function, a mask defect is viewed as a localized variation in the linewidth of the mask. The printing of a mask defect therefore depends strongly on the slope of the pattern transfer function. Defects smaller than 200 nm on the mask already cause a significant linewidth variation on the wafer, if those defects are in a regular array of 250 nm lines/300 nm spaces or in 300 nm contact holes. Lithogrpahy in a manufacturing environment means to deliver the designed pattern over large areas using real masks. We discuss our strategies of how we try to minimize the influence of mask irregularities in 0.25 micrometers lithography for the development of the 256M DRAM. Although certain improvements are possible, the nonlinearity of the pattern transfer function at low k obviously demands extremely tight mask specifications beyond the limits of current tools and processes.
As the competitive pressures of the semiconductor industry drive to feature sizes below 250 nanometer, unconventional imaging approaches are being considered in order to preserve the cost effectiveness of optical lithography. To achieve minimum feature size with a usable process window, phase shift masks, off-axis illumination, and ArF lithography have been investigated with varying degrees of success. Unfortuanely, the maturity and flexibility of such techniques are questionable at this time. This paper investigates the extendibilty of traditional imaging approaches for use in the sub 250 nanometer regime. Aerial image simulations were used to set expectation levels by increasing lens numerical aperture versus prior state of the art exposure systems. Experimental data was then generated with an advanced 0.6 NA excimer laser based step and scan exposure system. Single point per field comparisons are made between simulations and experimental data covering linearity, depth of focus, and exposure dose window for feature sizes between 250 nanometers and 200 nanometers. In addition, data reviewing the ability to extend such performance across a 25 mm by 33 mm field size is reviewed.
At low k1 factors, optical proximity correction (OPC) is used to correct line size such that what is delivered by the lithography process is closer to the design dimension than an uncorrected process would deliver. OPC is usually derived for perfect masks and exposures. Random variation of the mask critical dimension (CD), wafer exposure latitude, and wafer defocus are examined for their effects on an OPC mask. Expected CD variation in the aerial image is given for each of these variables. Examining these variables will also give insight as to how fine an OPC can realistically be obtained, and how fine a grid size is needed in the manufacture of the mask.
Lithographic performance has typically been evaluated at a single point within the stepper field. However, this evaluation method does not completely provide the total lithographic performance on a chip because of variations introduced by the stepper as well as the reticle. In this paper, the evaluation method and characteristics of across-field performance are shown through the use of electrical line width measurements and exposure-defocus (ED) analysis. The across-field performance is analyzed by both the average process window and the common process window for two resolution enhanced photolithography techniques: phase-shifting mask (PSM) and off-axis illumination (OAI). The average process window corresponds to a single-point evaluation while the common process window includes all lithographic fluctuations across the field. Consequently, the common process window is much smaller than the average process window. Moreover, to consider the effect of mask critical dimension (CD) deviation on lithographic performance, a mask CD deviation enhancement factor (MEF) is introduced. By MEF correction, the contribution of mask CD deviation to common window degradation is obtained.
Specifications for photomasks to be used to print 0.25 micrometers structures have to be much tighter than mask specifications for today's most advanced 0.5 micrometers technologies. As optical lithography works closer to its resolution limit, line shortening, increased susceptibility to errors in mask manufacturing, and enhanced printing of mask defects has to be taken into account. Phase shift masks improve the process window of lithography and provide therefore more room for selective mask biasing. However, the additional parameters inherent to particular phase shift mask types (phase shift, transmission uniformity for attenuated phase shift masks, rim uniformity for rim-phase shift masks) contribute to the total error budget and need therefore to be controlled to very tight tolerances, too.
The phase shifting mask technology has quickly progressed from the exploratory phase to a serious development phase. This requires high resolution measurement techniques to quantify experimental results to optimize the designs. This paper describes a set of electrical linewidth measurement testsites which covers all five representative lithographic features in combination of dark-field and light-field patterns, positive and negative resists. The testsites can investigate binary intensity mask, attenuated, alternating, subresolution-assisted, rim, unattenuated, edge, and covered edge phase shifting masks. All testsites can be used with a single-level wafer exposure. There is no need to remove extra shorts or opens induced by uncovered phase shifters.
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