This paper presents an innovative use of machine learning (ML) to improve etch modeling by integrating monotonic machine learning methods with ML-based contour metrology. Unlike traditional methods that rely on single gauge-based data, our approach leverages comprehensive contour data extracted from SEM images to predict etching biases. It handles large datasets efficiently and adapts dynamically to new data. A primary element of our strategy involves constructing a retargeting layer with etch bias, derived from features at multiple sites or points of interest (POIs) on a reference layer which is generated with a fuzzy clustering model. These features and their corresponding etch biases serve as training data for our semi-supervised model which will be used for prediction on large scale designs.
Siemens EDA (Mentor) has published their pioneering work on matrix OPC at SPIE before, in the same title but part I and II. Based on this work, an OPC feature MatrixOPC has been developed at Siemens EDA (Mentor). The MatrixOPC feature is now used by customers in production recipes routinely. However, this work was only focused on rectilinear OPC or Manhattan masks. In this paper, we present our current effort in generalizing the rectilinear matrix OPC to the curvilinear mask setting and to curvilinear OPC. Our initial test with a particular test case shows a promise that the new version, curvilinear matrix OPC and still under development, may also become a useful supplemental instrument for our curvilinear OPC solutions, compared to the curvilinear OPC practices without it. In this paper we will define the Jacobian matrix for the curvilinear mask setting, and compare the Jacobian matrices obtained from the brute-force definition and from our fast approximation algorithm, by comparing their total differentials. We also compare the OPC results from regular curvilinear OPC and matrix OPC with a fast approximated Jacobian.
Traditional approaches to quantifying stochastic EUVL variability for the use in stochastic-aware OPC correction and verification algorithms are tested against the stochastic EUVL via failure probability calculation by the Calibre stochastic model. The purpose is to check if these simplified approaches, based on the image metrics (e.g., NILS) or PV band parameters may provide an accurate failure probability prediction for a broad variety of layouts typical for the via layers of modern ICs. We also present the examples of verification of the Calibre stochastic model failure probability predictions against the brute force Monte Carlo trials.
The new high numerical aperture (NA) Extreme Ultraviolet Lithography (EUVL) with a NA of 0.55 is being developed at ASML, which is using an anamorphic projection system with the demagnification of 4× in xdirection and 8× in y-direction. Compared to the traditional 0.33NA EUV scanner with full-field image size of 26 × 33mm2, 0.55NA EUVL reduces the exposure field size to half-field (26 × 16.5mm2), due to this 8× demagnification in y-direction and the reticle size remaining unchanged (six-inch square). Therefore, in-die stitching between two exposures is needed for the applications requiring larger than half-field size. To achieve in-die stitching in practical applications at advanced node, performing model based optical proximity correct (OPC) is an essential step. Therefore, a complete process modeling and OPC flow is required. To build an accurate OPC model, the interaction effects between two stitching fields require some special considerations, such as aerial image interaction, optical proximity effect among the stitching patterns, mask absorber reflection, black border proximity effect, as well as the stray light from the neighboring fields effect. All these effects must be captured by specific models. In this paper, we will investigate the in-die stitching effects and solutions through simulation and wafer data. Thus, to collect the wafer proof data, various stitching test patterns have been designed and placed on imec test masks, and the wafer data will be obtained on imec 0.33NA EUV scanner.
Curvilinear(CL) mask shapes have showed better lithography performance, including improved process window, better PVband and MEEF compared to Manhattan mask. With the development of Multi-Beam-Mask-Writer (MBMW), the adoption of CL mask in production becomes reality.
However, there are multiple challenges associated with CL data, such as complex mask shape and large data volume. One of the most important challenges is to have a good set of Mask-Rule-Check(MRC) rules which is essential to achieve good OPC mask quality.
Calibre® OPCVerify has been developed for years to check CL shapes. Combining with existing checks, a full suite of CL MRC checks has been added. In this paper, we will present a fully integrated CL verification flow.
This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.
With the adoption of multi-beam mask writing (MBMW) technology, there is a strong drive to realize the maximum lithographic process window entitlement which can be obtained with curvilinear masks, including both SRAFs and main features. Inverse Lithography Technology (ILT) has always featured prominently in planning for such masks, as it can produce the ideal curvilinear patterns which represent the best possible solution. The runtime for ILT, however, remains too slow for full-chip logic manufacturing and this paper will review multiple alternative approaches which endeavor to produce similar output masks but with significantly faster runtime. Results will be shown for 3nm-node via and metal examples where full ILT, hybrid ILT and dense curvilinear OPC, hybrid curvilinear SRAF and dense curvilinear OPC, and machine learning approaches will be assessed for runtime and a variety of lithographic metrics. Overall, all solutions are shown to be considerably faster than full ILT, ranging between 4x (for hybrid ILT SRAF) to <100X improved runtime performance. Lithographic capability is characterized in terms of distributions of edge placement errors (EPE), PV Bands, and ILS/NILS. There are some minor differences between the various options, but given the pronounced runtime advantages over ILT, all are compelling options, delivering lithographic PW enablement close to the ideal ILT solution. For the model-based DNN, and Monotonic Machine Learning (MML) approaches, we will discuss the approach, challenges, and advantages associated with robust training to ensure the broadest possible pattern coverage.
Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].
To maintain good critical dimension control, optical proximity correction (OPC) has relied on fast compact models to capture the underlying lithography process in advanced nodes. Compact models have always been deterministic in the sense that they predict the average dimensions or contours on wafer. With the introduction of extreme ultraviolet (EUV) lithography, this approach breaks down due to large variabilities in EUV lithography processes. Recently, empirical correlations were found between this variability and imaging metrics, allowing the development of compact models. Such stochastic models have been used successfully to predict hotspots. In this paper an attempt is made to apply such stochastic models during OPC to reduce the number of stochastic failures. Different OPC strategies are applied on an advanced random logic and SRAM design, focusing on a via layer with a calibrated stochastic model. Through simulations, we show that the failure rate can be reduced by using a stochastic model during OPC, at the expense of edge placement error. However, when reducing the stochastic band width to match the process variation band width, no meaningful differences were observed between process-window OPC and stochastic OPC due to uniformity of pattern dimensions in sample layout.
The patterning requirements of next generation lithographic processes and the desire to keep manufacturing costs down have pushed the lithographers to explore the advantages of the curvilinear masks. Multiple studies backed by the experimental results have demonstrated the lithographic advantage of the curvilinear (CL) photomasks over the rectilinear (RL) approximations by showing improved MEEF, depth of focus (DoF) and common DoF (CDoF) for variety of patterns on the same mask, ILS and, as a result, process window (PW) of the CL masks over its close RL siblings [1,2]. Manufacturability of the CL masks has been limited due to the architecture of the Variable Shaped Beam (VSB) writers, which made it prohibitive from both mask data preparation (MDP) and mask writing perspective. The availability of Multi Beam Mask Writers (MBMW) has removed these roadblocks and brought introduction of the curvilinear masks much closer to reality. The development of novel approaches for MDP and Mask Proximity Correction (MPC) as it is demonstrated by Bork et al in [3] brought further advances in availability of the CL masks for high volume manufacturing (HVM). Traditionally the Inverse Lithography Technology (ILT) has offered the most potential to achieve significant lithographic advantage over RL masks but has suffered from very long data preparation runtimes which presented an additional hurdle for broad deployment in manufacturing. While various speed up options such as machine learning-based acceleration, and GPU processing [4,5] are being explored, the full chip ILT run time still represents significant challenge in the HVM world. This paper will concentrate on two OPC approaches that allow CL mask generation without run time penalties associated with full chip ILT processing. The first is based on a hybrid methodology that allows for generation of the CL mask shapes by using fast ILT-based algorithms for SRAF generation while the main features are controlled to allow for full chip processing within the reasonable time. The second approach is more appropriate for the memory applications where patterns are highly repetitive. Due to high level of repetition, it is acceptable to use full ILT correction carried over a small area of the chip and to utilize pattern matching (PM) methodologies to propagate both SRAFs and OPC-corrected features from unique to non-unique pattern placements. Such a methodology allows for the full ILT advantages in the highly critical memory array areas.
As the technology node gets smaller and smaller, the benefit from Sub-Resolution Assist Features (SRAF) becomes significant in EUV lithography which makes SRAFs a must-have tool for next generation beyond 7nm technology. When considering EUV specific effects, the metrics that need to be accounted for include Image Log-Slope (ILS), Process Variability (PV Band), common Depth of Focus (cDOF), and Image Shift (ImS) through focus. When these critical factors are accounted for during the EUV mask generation the optimization become much more complicated and challenging and necessitates the need for SRAFs beyond 7nm. SRAF helps enhance not only the PV Band, but more importantly helps boost the ILS, which is one of the key factors for improving stochastic effect in EUV. However, ILS is just one of the important image quality metric that we should focus on. For metal layers, Image Shift is another key factor which can have a big impact on overlay. ImS at the nominal condition could be compensated by Optical Proximity Correction (OPC), but image shift through focus can hardly be tuned by the main feature correction. The image shift through focus can be mitigated by SRAF insertion. Strong 3D mask effects can cause best focuses of different patterns to be far apart in EUV, which can cause an unusable cDOF even when the individual depth of focus values of all the patterns are not bad. SRAFs can be inserted to improve the individual depth of focus and align the best focuses together to help enhance the common process window. When taking account of various different EUV specific metrics mentioned above, then the most critical question for the next generation beyond 7nm is “How to define the cost function for mask optimization with SRAFs?” (Figure 1, EUV mask optimization flow for next generation beyond 7nm). In this study the image quality metrics including ILS, PVBand, cDOF, and ImS are evaluated. For each optimization schema using different cost functions, we examine the cost function metric and its impact on the other image quality metrics. We also present the potential trade-offs together with the analysis. Furthermore, multiple cross cost functions are defined for SRAF optimization and the results are analyzed accordingly. Both contact and metal layer patterns representing next generation beyond 7nm design rules are investigated. In our testing, symmetric standard sources from ASML NXE3400 is examined and the results are compared and analyzed.
As the EUV lithography is extending beyond 7nm technology, design to mask strategy becomes more complex. New challenges including advanced OPC and ILT in mask optimization, curvilinear masks, shrinking Mask Rule Checking (MRC), Sub-Resolution Assist Features (SRAF) generation and formation, and other complex mask geometries drive the needs to study this synergy from different stages of the flow from Optical Proximity Correction (OPC), Mask Process Correction (MPC), fracturing, to mask writing and inspection. In this study, different OPC and SRAF mask formations including curvilinear masks, controlled Manhattanized approximations of curvilinear masks, and conventional masks are generated. We illustrate whether curvilinear masks have any demonstrable lithographic benefits. A quantitative comparison of how the Manhattanization impacts mask formation. The image quality metrics such as Image Log Slope (ILS), Process Viability (PV) Band, and Depth of Focus (DOF) from various OPC mask flavors including different MRC settings and different mask forms are compared and discussed. The mask manufacturability study is conducted to identify any major challenges and approaches to minimize, including assessing the value and need for native curvilinear write tool support on a MultiBeam Mask Writer (MBMW) or a single beam Vector Shaped Beam (VSB) mask writer.
The next-generation beyond 7-nm node potentially requires the implementation of subresolution assist features (SRAF) with extreme ultraviolet (EUV) lithography. This paper aims at providing a clear SRAF strategy for the next-generation beyond 7-nm node designs through a series of experiments. Various factors are considered, including stochastic effects, three-dimensional (3-D) mask effects, through-slit effects, aberrations, and pixelated source mask optimization (SMO) sources. We consider process variability bands with a variety of process conditions, including focus/dose/mask bias changes and also the normalized image log-slope/image log-slope as our objective functions, to determine what the best SRAF solution is for a set of test patterns. Inverse lithography technology is implemented to optimize both the main feature (MF) mask and SRAF placement, in particular, asymmetric SRAF placement to balance the 3-D mask effects. SRAF can potentially mitigate image shift through-focus, i.e., nontelecentricity, caused by EUV 3-D shadowing effect. This shadowing effect is pattern-dependent and contributes to the overlay variation. As we approach the next-generation beyond 7-nm node, this image shift can be more significant relative to the overlay budget, hence, we further investigate the impact of SRAF placement to the image shift. Moreover, the center of focus shift due to the large 3-D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus and is evaluated using both metal and contact layer test cases. We study the source impact to SRAF insertion by experimenting with both a symmetric source (standard source) and an asymmetric source (SMO source). Finally, we understand the importance of using full flare map and full through-slit model (including aberration variation through-slit) in the MF correction. Furthermore, we evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next-generation beyond 7-nm node.
The next generation beyond 7nm node potentially requires the implementation of Sub-Resolution Assist Features (SRAF) with EUV lithography. This paper aims at providing a clear SRAF strategy for the next generation beyond 7nm node designs through a series of experiments. Various factors are considered, including: stochastic effects, 3D mask effects, through-slit effects, aberrations, and pixelated SMO sources.
EUV has 13.5nm as its wavelength, which is much smaller than the wavelength used in ArF lithography, and this gives very different imaging challenges compared to the ArF case. Due to the small wavelength and numerical aperture (NA) of the current EUV tools, depth of focus is not as significant of a concern as in DUV. Instead, EUV lithography is severely challenged by stochastic effects, which are directly linked to the slope of the intensity curve. DUV SRAF has been shown to be a powerful tool for improving NILS/ILS, as well as DOF, and here we explore how that translates into EUV imaging. In this paper, we consider Process Variability (PV) Bands with a variety of process conditions including focus/dose/mask bias changes and also the NILS/ILS as our objective functions, to determine what the best SRAF solution is for a set of test patterns. We have full investigations on both symmetric SRAF and asymmetric SRAF.
SRAF can potentially mitigate image shift through focus, i.e. non-telecentricity, caused by EUV 3D shadowing effect. This shadowing effect is pattern dependent and contributes to the overlay variation. As we approach the next generation beyond 7nm node, this image shift can be more significant relative to the overlay budget, hence we further investigate the impact of SRAF placement to the image shift. Moreover, the Center of Focus shift due to the large 3D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus. We study the change by adding SRAF using both a symmetric source (standard source) and an asymmetric source (SMO source). Once SRAF is inserted for the test patterns, the common process window is plotted to compare the solutions with and without SRAF.
Finally, we understand the importance of using full flare map and full through slit model (including aberration variation through slit) in the main feature correction, but in this paper, we will further evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next generation beyond 7nm node.
Process window OPC (PWOPC) is widely used in advanced technology nodes as one of the most important resolution enhancement techniques (RET).1 PWOPC needs to consider not only edge placement error (EPE) from nominal condition simulations, but also constraints based on process variation simulations, such as pinch and bridge related requirements based on process variation band (PVBAND). Those constraints can be challenging to meet as feature size continues to shrink in advanced nodes.
In this paper a novel matrix retargeting based PWOPC was developed to find optimal OPC solutions by solving constraints-based matrix and applying minimal retargeting as needed.2 Experiment results showed enhanced process window and reasonable performance.
In this paper advanced OPC (Optical Proximity Correction) methods, additional with assistant features, and non-obvious
methods were implemented to correct aberrations caused by aggressive illuminations in order to optimize the shape of
the finger tips. OPC model and simulations were verified using 2D verification method.
KEYWORDS: Manufacturing, Microelectronics, Computer aided design, Semiconductors, Design for manufacturability, Yield improvement, Nanoelectronics, Lithography, Field effect transistors, Control systems
A perspective is presented on how the semiconductor integrated circuit industry has evolved and what we can expect over the next decade or two. However, this 'forecast' is given in only the broadest sense, to make it relatively independent on innovations and discoveries that are likely to strongly shape the industry over this time period. Rather, trends are examined, as well as general 'tools' that will undoubtedly be important in advancing from our present microelectronics era to our presumable future in nanoelectronics.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.