The standard tantalum mask gives strong 3D electromagnetic effects, hence, its utilization in foundries to enable further downscaling to the A14 node might reach its limits even with the help of high NA EUV scanners (with 0.55 numerical aperture “NA”). The use of alternative mask absorber materials together with inverse lithography techniques (ILT), such as source mask optimization (SMO), can improve printing of metal logic layers with a target pitch of 20 and 24nm. This is possible due to thinner mask absorber thickness (around 40nm instead of 60nm for Ta-based mask) and due to different EUV optical properties of the mask material causing a different behavior of the light that is reflected by the masks. To better mitigate the light behavior during and after reflection from the mask, materials covering a good portion of the n-k graph (EUV refractive index, n, by EUV extinction coefficient, k) were chosen. The study proposes a comparison between baseline (Ta-based mask) and five new mask absorber candidates, ranging from three materials with lower refractive index and varied extinction coefficient (“low-n” with low-, mid-, and high-k), and two candidates with higher extinction coefficients (“highk” with mid- and high-n). This paper contains simulation results with the Siemens EDA Calibre tool and demonstrates theoretical proof that alternative mask materials bring significant gain when compared to the tantalum-based mask absorber. Firstly, we optimized the source and aerial image intensity threshold on a set of predefined clips (with SMO techniques). Secondly, we applied ILT techniques to correct for the full chip mask based on a horizontal layout of a metal logic layer on imec’s roadmap. We then compare the tantalum-based mask with the alternative masks using imaging criteria, such as DoF (depth of focus), NILS (Normalized Image log slope), EPE (edge placement error), pattern shifts through focus, process variation band, source telecentricity errors, and MEEF (mask error enhancement factor) on a variety of features in the metal logic clip to maximize the overall process window.
This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.
Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].
Tuning the spectrum of a scanner’s excimer laser light source is a well-known technique to achieve improved depth of focus (DOF) for an exposure. Previous studies have focused on the imaging improvement capabilities of readily available spectral shapes such as Gaussian E95 single peak width, as well as dual-peak spectral shapes where the spacing of the peaks can be varied. It is commonly known that adjustments in the laser spectrum must be carefully considered since exposure latitude (EL) can also be reduced as DOF is increased. By carefully engineering the laser’s spectrum, DOF can be maximized with very little impact to exposure latitude. Undesirable speckle contrast can also be reduced as laser bandwidth is increased. Traditionally, these approaches have been used to improve DOF of thick resist applications such as CMOS image sensors. Other areas such as NAND Flash have introduced laser spectrum engineering (SE) to compensate for topography effects between periphery and array regions. Recently, advances in laser hardware have enabled new and unique spectral shapes to be used for imaging. In this paper, we explore the various spectral profiles possible on the latest Gigaphoton GT66A ArFi light sources. New applications of these spectrum shapes are considered for foundry logic-type levels. First, a representative 14nm-node logic layer is considered. Source Mask Optimization (SMO) is performed while various widths of spectral profiles are used as input, such as traditional E95 Gaussian profiles, dual-peak, and flat top. By accounting for the laser spectrum during SMO, common DOF can be improved by ≥ 20% without a noticeable decrease in exposure latitude. The SMO sources and optimized masks are also different from each other and the nominal cases, depending on the spectral distribution used. Next, we explore simultaneously optimizing the laser spectrum, source, and mask in an experimental SMO+SE. Spectra can be constrained to keep symmetric profiles about the 193nm center point. Improved lithographic performance can result from the application of programmable laser spectra combined with pixelated sources and inverse lithography (ILT).
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