Device scaling has not only driven the use of measurements on more complex structures, in terms of geometry, materials, and tighter ground rules, but also the need to move away from non-patterned measurement sites to patterned ones. This is especially of concern for very thin film layers that have a high thickness dependence on structure geometry or wafer pattern factor. Although 2-dimensional (2D) sites are often found to be sufficient for process monitoring and control of very thin films, sometimes 3D sites are required to further simulate structures within the device. The measurement of film thicknesses only a few atoms thick on complex 3D sites, however, are very challenging. Apart from measuring thin films on 3D sites, there is also a critical need to measure parameters on 3D sites, which are weak and less sensitive for OCD (Optical Critical Dimension) metrology, with high accuracy and precision. Thus, state-ofthe-art methods are needed to address such metrology challenges. This work introduces the concept of Enhanced OCD which uses various methods to improve the sensitivity and reduce correlations for weak parameters in a complex measurement. This work also describes how more channels of information, when used correctly, can improve the precision and accuracy of weak, non-sensitive or complex parameters of interest.
In this paper we propose a “film on grating” (FoG) measurement technique using spectroscopic ellipsometry (SE) that can enable sub-Ångstrom level precision for multi-layer film thickness measurement on topographies that closely approximate the device structure. FoG follows the industry trends to 'measure what matters' and provides thickness measurement data from patterned structures that has much stronger correlation to actual device performance. We also explore the impact of deviations in the film stack that can appreciably alter the device performance. One of the key device performance metrics that we will investigate is the leakage current, which is highly sensitive to process variations or defectivity. Measuring both the thickness and the bandgap of the HK dielectric permits excellent correlation with leakage current as determined by electrical testing of the device. The ability to predict electrical parameters effectively will greatly accelerate learning cycles during process development and can enable real time product control on existing inline metrology tools.
Advanced technology nodes, 10 nm and beyond, employing multipatterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. A self-aligned quadruple patterning (SAQP) process is used to create the fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bears the compounding effects from successive reactive ion etch and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes, which work on an assumption that there is consistent spacing between fins. In SAQP, there are three pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology, such as transmission electron microscopy. We will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.
Complexity of process steps integration and material systems for next-generation technology nodes is reaching unprecedented levels, the appetite for higher sampling rates is on the rise, while the process window continues to shrink. Current thickness metrology specifications reach as low as 0.1A for total error budget – breathing new life into an old paradigm with lower visibility for past few metrology nodes: accuracy. Furthermore, for advance nodes there is growing demand to measure film thickness and composition on devices/product instead of surrogate planar simpler pads. Here we extend our earlier work in Hybrid Metrology to the combination of X-Ray based reference technologies (high performance) with optical high volume manufacturing (HVM) workhorse metrology (high throughput). Our stated goal is: put more “eyes” on the wafer (higher sampling) and enable move to films on pattern structure (control what matters). Examples of 1X front-end applications are used to setup and validate the benefits.
Advanced technology nodes, 10nm and beyond, employing multi-patterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. Self-Aligned Quadruple Patterning (SAQP) process is used to create the Fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bares compounding effects from successive Reactive Ion Etch (RIE) and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes which work on an assumption that there is consistent spacing between fins. In SAQP there are 3 pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology such as Transmission Electron Microscopy (TEM). In this paper we will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.
Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets requirements, especially at 10nm node due to the 3-d geometry of devices and tight process budget. It has become necessary to measure and control each layer in the gate stack before and after dielectric and metal gate deposition sequences. A typical gate stack can have 5-7 layers including the interfacial layer, high-k dielectric, metal gate stack, work function layers, and cap layers. Similarly, PMOS channel strain is controlled using a graded SixGe1-x stack grown epitaxially over fins in the source/drain regions. This graded stack can have 2-4 layers of different thicknesses and Ge concentrations. This paper discusses the benefit of using spectroscopic ellipsometry with multiple angles of incidence to accurately and precisely determine the thickness of individual layers in critical gate layer stacks at various process steps on planar and grating surfaces. We will also show the benefit of using an advanced laser-based ellipsometer, for ultra-precise measurement of the gate interfacial layer oxides.
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