As the cell size of memory devices continues to shrink, tighter On-Product Overlay (OPO) specifications toward a 1nm OPO budget are required. EUV (extreme ultraviolet lithography) production was adopted in 2019 and the next lithography development known as High NA EUV will fulfill market demand beyond 5nm and 3nm process nodes. High NA EUV requires shrinking the scribe line from 50μm to 40μm, which results in new requirements for the target size to be smaller than the current size μDBO (16x16μm) and AIM (24x24μm) targets. The reduction in the scribe line is certainly beneficial to chipmakers for wafer real estate and yield. For metrology measurements in high-volume manufacturing (HVM), the main optical overlay (OVL) metrology usually uses imaging-based overlay (IBO) technology, while in other cases diffraction-based overlay (DBO) and scatterometry-based overlay (SCOL) are used. All methods (IBO, DBO, and SCOL) face the same challenge of target size reduction. For instance, IBO targets require a restricted number of grating bars. Most importantly, the smaller the target size, the less kernel information affects measurement quality. The spot size of DBO is larger than the target size, so it increases noise sources from the target's surroundings and affects the OVL accuracy. SCOL technology offers several advantages over IBO and DBO when measuring small targets since the spot size in SCOL is smaller and the spot navigation has a higher control mechanism. In this paper, we present a method called parallax to measure a single-cell overlay using pupil information. We will demonstrate three values: First, the target size can be reduced by up to half. Second, the measurement time is improved by saving navigation time from cell to cell. Third, the optical z-value for each point is reported along with OVL measurements. Additionally, the feasibility of single-cell OVL measurement and optical z-value is demonstrated as KPIs for process control.
KEYWORDS: Overlay metrology, Semiconducting wafers, Advanced process control, Scanners, Scatterometry, Process control, Signal processing, Metrology, Control systems, Optical parametric oscillators
As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.
Total measurement uncertainty (TMU) is a commonly used key performance indicator (KPI) for tool-induced error in metrology systems. Several definitions of TMU are being used today for overlay metrology (OVL), with the leading definition being the root-sum-square (RSS) of three other KPIs: the wafer mean Tool Induces Shift (TIS𝜇), the wafer variability of TIS (TIS3σ), and the OVL measurement reproducibility (OVL precision). A multitude of TIS management methods has been developed and implemented over the years for calibrating out the raw TIS from OVL. With these TIS management methods in place, the use of the raw TISμ and TIS3σ in TMU no longer serves as a good characterization of the total tool-induced error. In this paper, we describe a procedure for evaluating the actual, post-TIS management, OVL Metrology TMU through the introduction of two new wafer level indicators: the effective wafer means TIS (eTISμ), and the effective wafer TIS variability (eTIS3σ).
As DRAM technology continues to evolve, advanced nodes shrink the device dimensions and raise the requirements for on-product overlay control to reduce residual error. Increased process complexity also demands tighter accuracy and robustness in metrology control, which necessitates new and innovative metrology enhancements and methods. Scatterometry-based overlay (SCOL®) metrology is a unique overlay metrology architecture that uses angle-resolved pupil imaging for overlay analysis and calculation. KLA’s SCOL metrology system offers wide-spectrum tunable laser and multi-wavelength (MWL) illumination patterns along with custom-designed advanced algorithms that provide multiple measurement conditions to meet unique layer and target requirements. This paper demonstrates improved overlay metrology accuracy and residual error on DRAM FEOL critical layer with SCOL technology. Multiwavelength and rotated quadrupole (RQ) illumination in the metrology tool are utilized to provide significantly improved residuals compared with the traditional single-wavelength (SWL) and on-axis illumination.
In recent technology node manufacturing processes, on-product overlay (OPO) is becoming increasingly more important. In previous generations, the optimization of the total measurement uncertainty (TMU) itself was sufficient. However, with the use of modern technologies, target asymmetry-related measurement inaccuracy became a significant source of error, requiring new methods of control. This paper presents a machine learning (ML) based algorithm that reduces inaccuracy in misregistration measurements of the after-develop inspection (ADI) optical overlay (OVL). The algorithm relies on numerous features that were extracted from the OVL tool camera images, accuracy metrics derived from OVL computation, and other metadata. It is trained to estimate OVL measurement inaccuracy and produce corrected OVL per site. The ground truth of the ML model can include either internal or external OVL values. In the former case, the model is trained using wafer modeling errors (a.k.a. residuals), implying that these are a good indicator of target inaccuracy, which is a commonly used assumption. In the latter case, the model is trained using external overlay as the reference. If an accurate external reference overlay measurement exists, this option can be the most accurate. In both cases, the algorithm produces corrected OVL values. This study shows that for both ground truth options, the suggested method reduces inaccuracy and wafer modeling residuals in ADI optical OVL metrology measurements. The results were obtained by experimenting on production wafers from DRAM critical layers at SK Hynix. All the measurements were taken using an imaging-based overlay (IBO) technique and were validated by scanning electron microscope (SEM) measurements of the same wafers.
In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM)[1] allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.
With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter, driving requirements for on-product overlay performance below 2.5nm and CD uniformity requirements below 0.8nm. Achieving such performance levels will not only need performance optimization of individual tools but a holistic optimization of all process steps. This paper reports on the first step towards holistic optimization – co-optimized performance control of scanner and etch tools. In this paper we evaluate the use of scanner and etcher control parameters for improvement of after final etch overlay and CD performance. The co-optimization of lithography and etch identifies origins of the variabilities and assigns corrections to corresponding tools, handles litho-etch interactions and maximizes the correction capability by utilizing control interfaces of both scanner and etch tools in a single control loop. The product aims to improve total variability measured after etch as well as fingerprint matching between tools. For CD control we co-optimize the dose corrections on the lithography tool with the temperature corrections on the etcher. This control solution aims to correct CD variabilities originating at deposition, lithography and etcher. For overlay we co-optimize the overlay inter and intra-field grid interfaces on the scanner with the wafer edge ring height compensation on the etcher. The evaluation of both CD and overlay control solutions is performed for the 2xnm DRAM node of SK hynix DRAM group. YieldStar in-device metrology after core etch was used for CD control. On wafer verification showed an improvement of 23% of the total CD variation. In-device metrology after final etch was user for overlay control. Evaluation showed 35% improvement in total overlay variability due to scanner-etch co-optimization.
To support the manufacturing of DRAM semiconductors for next and future nodes, there is a constant need to reduce the overlay fingerprints. In this paper we evaluate algorithms which are capable of decoupling wafer deformation from mark deformation and extrapolation effects. The algorithms enable lithography tools to use only the wafer deformation component in the alignment feedforward correction. Therefore improving the (wafer to wafer) overlay. First results will be shared showing improvement of wafer to wafer variation in high-volume manufacturing environment.
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