Dr. Carl P. Babcock Profile

Dr. Carl P. Babcock

Senior MTS, OPC Development at GlobalFoundries

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Publications (10)

Proceedings Article | 18 March 2015 Paper

Hybrid OPC flow with pattern search and replacement

Piyush Verma, Shikha Somani, Yang Ping, Piyush Pathak, Rani Ghaida, Carl Babcock, Fadi Batarseh, Jingyu Wang, Sriram Madhavan, Sarah McGowan

Proceedings Volume 9426, 942611 (2015) https://doi.org/10.1117/12.2087094

KEYWORDS: Optical proximity correction, Photomasks, SRAF, Photovoltaics, Model-based design, Very large scale integration, Optical lithography, Data modeling, Image classification, Library classification systems

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Proceedings Article | 28 March 2014 Paper

Robust and automated solution for correcting hotspots locally using cost-function based OPC solver

Carl Babcock, Dongok Yang, Sarah McGowan, Jun Ye, Bo Yan, Jianhong Qiu, Stanislas Baron, Taksh Pandey, Sanjay Kapasi, Chris Aquino

Proceedings Volume 9053, 90530Z (2014) https://doi.org/10.1117/12.2046662

KEYWORDS: Optical proximity correction, SRAF, Source mask optimization, Optical lithography, Photovoltaics, Neodymium, Lithography, Model-based design, Resolution enhancement technologies

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In previous work¹, we introduced a new technology called Flexible Mask Optimization (FMO) that was successfully used for localized OPC correction. OPC/RET techniques such as model-based assist feature and process-window-based OPC solvers have become essential for addressing critical patterning issues at 2× and lower technology nodes. With an FMO flow, critical patterns were identified, classified and corrected in localized areas only, using advanced techniques. One challenge with this flow is that once the hotspots are identified, a user still has to come up with OPC solutions to address the hotspots. This process can be cumbersome and time consuming as different types of hotspots with new designs may require different recipes, causing delays to tapeout. What is required is a robust, powerful and automated OPC technique that can handle various types of hotspots, so an automatic hotspot correction flow can be established. In this work, we introduce a new cost-function-based OPC technique called Co-optimization OPC that can be used to correct various types of hotspots with minimum tuning effort. In this approach, the OPC solver simultaneously solves for all the segments in a patch including main and sub-resolution assist features (SRAF), applying additional user-defined cost function constraints such as MEEF, PV band, MRC and SRAF printability. Unlike conventional OPC solvers, Cooptimization solvers can also move and grow SRAFs, which further improves the process window. The key benefit of the Co-optimization OPC solution is that it can be used in a standard recipe to resolve many different hotspots encountered across various designs for a given layer. In this study, we demonstrate that Co-optimization OPC can be successfully used to address various types of hotspots across designs for selected 2× nm node line/space layers, as an example. These layers have been particularly challenging as they use single-exposure lithography with k1 around 0.3. Aggressive RET solutions are required to address the patterning challenges for this layer. Finally, we will report on implementation of the Co-Optimization OPC Recipe within the FMO framework for hotspot correction.

Proceedings Article | 13 March 2012 Paper

Source mask optimization methodology (SMO) and application to real full chip optical proximity correction

DongQing Zhang, GekSoon Chua, YeeMei Foong, Yi Zou, Stephen Hsu, Stanislas Baron, Mu Feng, Hua-Yu Liu, Zhipan Li, Jessy Schramm, T. Yun, Carl Babcock, Byoung IL Choi, Stefan Roling, Alessandra Navarra, Tanja Fischer, Andre Leschok, Xiaofeng Liu, Weijie Shi, Jianhong Qiu, Russell Dover

Proceedings Volume 8326, 83261V (2012) https://doi.org/10.1117/12.916614

KEYWORDS: Source mask optimization, Optical proximity correction, Semiconducting wafers, Lithography, Electroluminescence, Scanning electron microscopy, Finite element methods, Etching, Critical dimension metrology, Image processing

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Proceedings Article | 17 October 2008 Paper

Double dipole RET investigation for 32 nm metal layers

Carl Babcock, Yi Zou, Derren Dunn, Zachary Baum, Zengqin Zhao, Itty Matthew, Pat LaCour

Proceedings Volume 7122, 71220R (2008) https://doi.org/10.1117/12.801789

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Photomasks, Critical dimension metrology, Metals, Fiber optic illuminators, Printing, Algorithm development, Detection and tracking algorithms

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Proceedings Article | 27 March 2007 Paper

Methods and factors to optimize OPC run-time

A. Dave, C. Babcock, S. McGowan, Y. Zou

Proceedings Volume 6520, 65203Z (2007) https://doi.org/10.1117/12.714182

KEYWORDS: Optical proximity correction, Data modeling, Calibration, Computer simulations, Statistical analysis, Process modeling, Photomasks, Mathematical modeling, Optimization (mathematics), Image processing

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With the increasing complexity of design and the shrinking of technology nodes, optical proximity correction has become an integral part of IC fabrication. Pattern fidelity is the baseline for any accurate OPC model. Calibrated process models are used to make iterative pattern adjustments over a fragmented design to align simulated images and the target layout. More and more advanced modeling techniques are deployed for accurate prediction of complicated 1D and 2D structures. As such, more aggressive layout situations must be taken into consideration for different process and OPC aspects such as optimization of process window, contrast, MEEF, OPC convergence, and many more. However along with different process optimizations, the mask complexity increases and the OPC run-time is also adversely affected. Often, it has been noticed that the OPC model accuracy is restricted by long OPC run-times. The variation in OPC runtime could be due to many factors, including number of finitely sized segments, multiple iterations of edge movements & simulations, convergence, multiple process conditions, step size, sitelength, model complexity, etc. Integration of fast and accurate analysis is needed to address the growing complexity of OPC solutions. We present here different approaches for OPC run-time improvement. A methodology is prepared to investigate accurate OPC models with fast runtimes. Additionally, proper selection of fragmentation, simulation sitelength, and number of iterations can be modified to achieve significant improvement in computation speed. The variation in run-time is assessed for different approaches listed above with an emphasis on OPC accuracy. Statistical analysis is used to measure image parameters and edge placement errors (EPE) for various experiments and the output is the measurement and plotting of accuracy versus run-time. This paper will present those results and suggest best practices for OPC run-time improvement that can be incorporated as a part of an OPC model building and OPC qualification flow.

Proceedings Article | 29 June 1998 Paper

Comparisons of critical parameters for high- and low-activation-energy deep-UV photoresists

Will Conley, Carl Babcock, Nigel Farrar, Hua-Yu Liu, Bill Peterson, Kazuo Taira

Proceedings Volume 3333, (1998) https://doi.org/10.1117/12.312425

KEYWORDS: Photoresist materials, Chemistry, Etching, Lithography, Manufacturing, Deep ultraviolet, Silicon, Microelectronics, Resistance, Metals

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Proceedings Article | 29 June 1998 Paper

Real-time amine monitoring and its correlation to critical dimension control of chemically amplified resists for sub-0.25-um geometries

Will Conley, Carl Babcock, John Lilygren, Clifford Sandstrom, Nigel Farrar, John Piatt, Devon Kinkead, William Goodwin, Oleg Kishkovich, John Higley, Phil Cate

Proceedings Volume 3333, (1998) https://doi.org/10.1117/12.312479

KEYWORDS: Critical dimension metrology, Contamination, Photoresist materials, Chemically amplified resists, Manufacturing, Phase modulation, Calibration, Deep ultraviolet, Semiconducting wafers, Head-mounted displays

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Proceedings Article | 1 June 1992 Paper

Correlation of Si wafer FTIR spectra with wafer temperatures and resist durability variations in plasma etching processes

Gregory Luckman, Carl Babcock, Helen Maynard, Chris Gamsky, James Taylor

Proceedings Volume 1672, (1992) https://doi.org/10.1117/12.59750

KEYWORDS: Semiconducting wafers, FT-IR spectroscopy, Etching, Plasma etching, Silicon, Reflection, Reflectivity, Plasma, Electrodes, Photoresist processing

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Proceedings Article | 1 June 1991 Paper

Process latitude measurements on chemically amplified resists exposed to synchrotron radiation

Carl Babcock, James Taylor, Monroe Sullivan, Doowon Suh, Dean Plumb, Shane Palmer, Amanda Berry, Karen Graziano, Theodore Fedynyshyn

Proceedings Volume 1466, (1991) https://doi.org/10.1117/12.46413

KEYWORDS: X-rays, X-ray lithography, Photomasks, Synchrotron radiation, Semiconducting wafers, Synchrotrons, Chemically amplified resists, Photoresist processing, Silver, Standards development

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