High NA anamorphic EUV scanner has anamorphic optics with 8x demagnification in y direction and thus twice smaller exposure fields 26x16.5 mm2. In-die stitching may be required in order to create dies larger than High NA exposure field. In this work we consider stitching of vertical lines and spaces (LS) and establish methodology of stitching evaluation including detailed contour metrology at stitch, across wafer performance, process window and contrast metrics and sensitivity to single layer overlay between two stitched fields.
High NA EUV lithography has become a reality. The high NA EUV scanner (EXE:5000) produces exposure fields of 26x16.5 mm2 which is twice smaller than standard fields on other scanners. For certain use cases (e.g. when a die is larger than the High NA field) stitching between two exposure fields might be required. Stitching of vertical lines across two exposure fields has already been demonstrated in several publications. In this publication, we pay attention to photomask related aspects of stitching which are multifold. We draw attention to the need for mask resolution enhancement which will enable advanced OPC at stitching. We will show stitching behavior on both Tantalum and low-n masks and demonstrate low-n absorber reflectivity suppression by means of sub-resolution gratings which is required for stitching. We explore the behavior of the exposure field black border (BB) edge and formulate recommendations for specifications on BB edge control as well as pattern placement and pattern fidelity at the black border. Finally, we conclude that the mask performance is a key enabler of High NA stitching.
In this publication, we consider stitching enablement for High NA EUVL, specifically ‘zooming in’ on vertical line stitching used to create a physical connection between fields on wafer. We discuss stitching CD metrology and analysis using experimental and simulation results for pitch 36 nm dense lines. Experimental results were obtained on the NXE:3400B scanner at imec. CD uniformity across wafer and through slit are investigated as well as the impact from image to image overlap variation and the contribution of reticle CD errors and mask 3D shadowing. In the previous publications, we gave an overview of stitching challenges and various interactions in the stitching zone. In this publication, we focus on the aerial image interaction. Along a stitched vertical line, there are variations in CD creating a certain CD profile. These CD variations were modeled in a rigorous simulator but also observed experimentally. In order to characterize this behavior, we perform CD profile metrology at the stitch. We investigate the root causes of CD variability at the stitch and propose control mechanisms of stitching optimization. A key control mechanism being optical proximity correction (OPC) as well as overlay control.
An increased interest to stitching for High NA EUVL is observed; this is driven by expected higher demand of larger size chips for various applications. In the past a recommendation was published [1] to have 1-5 um band where no critical structures of a High NA layer would be allowed. In [2], we have introduced new insights on at-resolution stitching. In this publication, we present new experimental results obtained on NXE:3400B scanner. In the past we showed NXE feasibility results of vertical lines and contact holes stitching at relaxed resolution (40-48 nm pitch) in a single wafer location. In this study we evaluate stitching behavior through slit at more aggressive resolutions (P36 and P24 lines / spaces). We provide an overview of interactions in the stitching area such as aerial image interactions, absorber reflection, absorber to black border transition, black border vicinity impact and show corresponding experimental and simulations results. We formulate initial requirements for black border edge placement control and show performance of new masks. For stitching with low-n masks, we discuss using sub-resolution gratings to suppress the elevated mask reflectivity. We show rigorous simulations of stitched images, its sensitivity to overlay errors and propose mitigation mechanisms for OPC. Finally, an overview of stitching enablers will be described: from improved reticle black border position accuracy and absorber reflectivity control to mask resolution and OPC requirements.
CD-based process windows have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD size, the acceptable number of printed defects has remained flat (Hint: Zero) as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD (“Critical Dimension”) process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A “defect-aware” process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and 3σ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare / correlate the measured CD process window results to the CD process margin.
We present an experimental study of pattern variability and defectivity, based on a large data set with more than 112 million SEM measurements from an HMI high-throughput e-beam tool. The test case is a 10nm node SRAM via array patterned with a DUV immersion LELE process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to a seemingly qualitative differences in defectivity. The large available data volume enables further analysis to reliably distinguish global and local CDU variations, including a breakdown into local systematics and stochastics. A closer inspection of the tail end of the distributions and estimation of defect probabilities concludes that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. We expect that the analysis methodology can be applied for defect probability modeling as well as general process qualification in the future.
In this paper, we discuss the metrology methods and error budget that describe the edge placement error (EPE). EPE quantifies the pattern fidelity of a device structure made in a multi-patterning scheme. Here the pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. EPE is computed by combining optical and ebeam metrology data. We show that high NA optical scatterometer can be used to densely measure in device CD and overlay errors. Large field e-beam system enables massive CD metrology which is used to characterize the local CD error. Local CD distribution needs to be characterized beyond 6 sigma, and requires high throughput e-beam system. We present in this paper the first images of a multi-beam e-beam inspection system. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As a use case, we evaluated a 5-nm logic patterning process based on Self-Aligned-QuadruplePatterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography.
In this paper we discuss the edge placement error (EPE) for multi-patterning semiconductor manufacturing. In a multi-patterning scheme the creation of the final pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. We describe the fidelity of the final pattern in terms of EPE, which is defined as the relative displacement of the edges of two features from their intended target position. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As an experimental test vehicle we use the 7-nm logic device patterning process flow as developed by IMEC. This patterning process is based on Self-Aligned-Quadruple-Patterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography. The computational metrology method to determine EPE is explained. It will be shown that ArF to EUV overlay, CDU from the individual process steps, and local CD and placement of the individual pattern features, are the important contributors. Based on the error budget, we developed an optimization strategy for each individual step and for the final pattern. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets.
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