As the limits of EUV single exposure direct printing are being explored there is a need for etch processes that can transfer small features and reduce defectivity. The implementation of high numerical aperture (NA) EUV scanner tool will allow for printing of sub-10 nm features in a single exposure. However, it reduces the depth of focus, thus requires thinner photoresist coatings. In preparation for high NA (0.55) we explore the etch implications of thin EUV photoresists. Here we show two different strategies for bridge defect reduction during etch and break elimination with selective deposition during the etch process.
EUV (extreme ultraviolet) lithography has been introduced in high volume manufacturing in 2019 and continuous improvements have allowed to push the lithographic performance to the limits of 0.33 NA single exposure. However, stochastic failures, pattern roughness and local critical dimension uniformity (LCDU) are still major challenges that need to be addressed to maintain node shrinkage and improve yield. Together with pitch downscaling, photoresist thickness is decreasing to prevent pattern collapse. A lower depth of focus is also expected with high NA EUV which might even thin further down the resist layer. Being able to transfer the patterns with good fidelity is therefore getting very challenging because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. A co-optimization of lithography processes, underlayers coating and etch processes is essential to further support the EUV patterning extension.
In this report, recently developed hardware and process solutions to stretch the limits of EUV patterning will be presented. The latest performance for both chemically amplified resists (CAR) and metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.
In the last years, the continuous efforts on the development of extreme ultraviolet lithography (EUVL) have allowed to push the lithographic performance of the EUV photoresists on the ASML NXE:3400 full field exposure tool, however, stochastic resist roughness, local critical dimension uniformity (LCDU) and pattern defectivity at nano-scale are still the major limiting factors of the lithographic process window of EUV resist when looking at sub-40nm pitches for both linespace (LS) and contact hole (CH) applications, especially in the low exposure dose regime [1]. To be effective during the lithographic EUV resist screening evaluation phase for such tight pitches, imec has implemented since 2018 [2] additional metrology analysis after resist development inspection (ADI) to further quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, and thus to improve the resist design at lithographic step in a faster manner. In this work, we have further extended the examination of the resist performance introducing additional metrology analysis after pattern transfer in a silicon nitride (SiN) substrate. We present the characterization results on 40nm and 36nm pitch staggered dense contact holes looking at both lithographic and etching knobs to mitigate the patterning process stochastic issues, confirming that the holistic litho-etch approach is an important and necessary step in the development path of EUV advanced patterning applications towards high volume manufacturing and high-NA EUV lithography.
Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.
EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps.
In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.
CD-based process windows have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD size, the acceptable number of printed defects has remained flat (Hint: Zero) as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD (“Critical Dimension”) process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A “defect-aware” process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and 3σ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare / correlate the measured CD process window results to the CD process margin.
Directed self-assembly (DSA) has been investigated over the past few years as the candidate for next generation lithography. Especially, sub 20nm line and space patterns obtained by chemo-epitaxy process are expected to apply to DRAM active area, Logic fin and narrow metal patterns. One of the biggest advantages of DSA lines is that the pattern pitch is decided by the specific factors of the block copolymer, and it indeed the small pitch walking as a consequence. However, the generating mechanism of the DSA pattern defect is still not cleared1-4 and the line edge roughness (LER) is not overtaken self- aligned quadruple patterning (SAQP).
In this report, we present the latest results regarding the defect reduction and LER improvement work regarding chemoepitaxy line and space pattern. In addition, we introduce the result of application of chemical epitaxy process to hole pattern.
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