The EUV High-NA scanner brings innovative design changes to projection optics, such as introducing center obscuration and the anamorphic projection optical system in the projection optics box (POB) to improve the system transmission while the NA is improved1 . These design changes need to be accounted for in the computational lithography software solutions, to ensure accurate modeling and optimization of the High-NA system performance on wafer. In this paper, we will systematically investigate the benefits of Source Mask Optimization (SMO) and mask only optimization to explore EUV High-NA full chip patterning solutions, where mask 3D effects (M3D) are captured in the optical modeling. The paper will focus on assessing the performance (including process window, depth of focus, normalized image log slope) of through-pitch 1D Line/space (L/S) patterns and 2D Contact/Hole (CH) patterns after aforementioned optimizations and demonstrate the impact of center obscuration on imaging. In addition, we will investigate the effect of sub-resolution assistant feature (SRAF) on High-NA patterning via comparing the optimized lithographic performance with and without SRAF. These findings will help determine the most optimal patterning solutions for EUV High-NA as we move towards the first High NA EUV insertion. The paper will also discuss the anamorphic SMO where MRC and mask description needs to change from wafer plane (1x1) to scaled reticle plane (1x2). The interfield stitching will also be briefly discussed in this paper.
Despite being crucial in an optical lithography process, “dose” has remained a relative concept in the computational lithography regime. It usually takes the form of a percentage deviation from a pre-identified “nominal condition” under the same illumination shape. Dose comparison between different illumination shapes has never been rigorously defined and modeled in numerical simulation to date. On the other hand, the exposure-limited nature of EUV lithography throughput demands the * illumination shape being optimized with the physical dose impact consciously taken into consideration. When the projection pupil is significantly obscured (as in the ASML EXE high NA scanner series), the lack of a proper physical dose constraint may lead to suboptimal energy utilization during exposure. In this paper, we demonstrate a method to accurately model the physical dose in an optical lithography process. The resultant dose concept remains meaningful in the context of a changing illumination pupil, which enables co-optimization of imaging quality and a throughput metric during the Source-Mask Optimization (SMO) phase, known as the Dose-Aware SMO. With a few realistic test cases we demonstrate the capability of Dose-Aware SMO in terms of improving EUV throughput via reducing the effective exposure time, in both regular and obscured projection systems. The physical dose modeling capability in computational lithography not only addresses those immediate challenges emergent from EUV throughput, but also opens the gate towards a broad class of exciting topics that are built upon physical dose, such as optical stochastic phenomena and so on.
An increased interest to stitching for High NA EUVL is observed; this is driven by expected higher demand of larger size chips for various applications. In the past a recommendation was published [1] to have 1-5 um band where no critical structures of a High NA layer would be allowed. In [2], we have introduced new insights on at-resolution stitching. In this publication, we present new experimental results obtained on NXE:3400B scanner. In the past we showed NXE feasibility results of vertical lines and contact holes stitching at relaxed resolution (40-48 nm pitch) in a single wafer location. In this study we evaluate stitching behavior through slit at more aggressive resolutions (P36 and P24 lines / spaces). We provide an overview of interactions in the stitching area such as aerial image interactions, absorber reflection, absorber to black border transition, black border vicinity impact and show corresponding experimental and simulations results. We formulate initial requirements for black border edge placement control and show performance of new masks. For stitching with low-n masks, we discuss using sub-resolution gratings to suppress the elevated mask reflectivity. We show rigorous simulations of stitched images, its sensitivity to overlay errors and propose mitigation mechanisms for OPC. Finally, an overview of stitching enablers will be described: from improved reticle black border position accuracy and absorber reflectivity control to mask resolution and OPC requirements.
Over the years, lithography engineers have continued to focus on CD control, overlay and process capability to meet node requirements for yield and device performance. Previous work by Fukuda1 developed a multi-exposure technique at multi-focus positions to image contact holes with adequate DOF. Lalovic2 demonstrated a fixed 2-wavelength technique to improve DOF called RELAX. The concept of multi-focal imaging (MFI) was introduced3 demonstrating two focal positions are created that are averaged over the exposure field, this wavelength “dithering” approach which can be turned on and off, thus eliminating any potential scanner calibration issues.
In this work, the application of this imaging method (1 exposure-2 focus positions) can be used in thick photoresist and high aspect ratio applications. An example of thick photoresist imaging is shown in figure 1. We demonstrate 5um line and space features in 10um of photoresist at 3 different imaging conditions. On the left, single focus imaging (SFI) at best dose and focus, the center image which is also SFI but at a defocus of +3.2um. On the right is MFI with 2 focus positions of 0 and 2.8um. Here we can see a significant improvement in the SWA linearity and image profile quality. A second example of high aspect ratio imaging using MFI is shown in figure 2. The aspect ratio of 13:1 is shown for this. The use of Tachyon KrF MFI source – mask optimization flow will be reviewed to demonstrate optimum conditions to achieve Customer required imaging to meet specific layer requirements.
Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.
Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).
Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.
ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.
In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.
Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational
lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but
require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers.
Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex
patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is
sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography
margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The
machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to
push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a
Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural
network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the
current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of
optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can
achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly
faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and
demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography
roadmap.
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