With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.
Over the years, lithography engineers have continued to focus on CD control, overlay and process capability to meet node requirements for yield and device performance. Previous work by Fukuda1 developed a multi-exposure technique at multi-focus positions to image contact holes with adequate DOF. Lalovic2 demonstrated a fixed 2-wavelength technique to improve DOF called RELAX. The concept of multi-focal imaging (MFI) was introduced3 demonstrating two focal positions are created that are averaged over the exposure field, this wavelength “dithering” approach which can be turned on and off, thus eliminating any potential scanner calibration issues.
In this work, the application of this imaging method (1 exposure-2 focus positions) can be used in thick photoresist and high aspect ratio applications. An example of thick photoresist imaging is shown in figure 1. We demonstrate 5um line and space features in 10um of photoresist at 3 different imaging conditions. On the left, single focus imaging (SFI) at best dose and focus, the center image which is also SFI but at a defocus of +3.2um. On the right is MFI with 2 focus positions of 0 and 2.8um. Here we can see a significant improvement in the SWA linearity and image profile quality. A second example of high aspect ratio imaging using MFI is shown in figure 2. The aspect ratio of 13:1 is shown for this. The use of Tachyon KrF MFI source – mask optimization flow will be reviewed to demonstrate optimum conditions to achieve Customer required imaging to meet specific layer requirements.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
All chipmakers understand that variability is the enemy of any process and that defectivity reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications put tight requirements on the DUV light source which will impact scanner imaging performance. Accurate identification of defectivity caused by on wafer hotspots along with the impact on process windows can be accomplished using existing industry capability. ASML’s Brion Lithography Manufacturing Checker (LMC) can be employed using existing models to perform hotspot analysis and verify process window impact for current and future 193 nm nodes.
In this presentation, we review a methodology to understand the effect bandwidth variation has on hotspot variability and defect variation on specific customer designs. Initial studies are based on a large number of customer specific 90 nm pitch layouts where bandwidth variability is investigated for its impact on hotspot variability. Defect density maps are generated from the baseline process with additional maps generated at various bandwidth ranges. This methodology has been applied to Cymer’s DynaPulse and new DynaPulse2 bandwidth control technologies demonstrating the impact that bandwidth variation can influence process defectivity levels.
Demand for mask process correction (MPC) is growing for leading-edge process nodes. MPC was originally intended to
correct CD linearity for narrow assist features difficult to resolve on a photomask without any correction, but it has been
extended to main features as process nodes have been shrinking.
As past papers have observed, MPC shows improvements in photomask fidelity. Using advanced shape and dose
corrections could give more improvements, especially at line-ends and corners. However, there is a dilemma on using
such advanced corrections on full mask level because it increases data volume and run time. In addition, write time on
variable shaped beam (VSB) writers also increases as the number of shots increases.
Optical proximity correction (OPC) care-area defines circuit design locations that require high mask fidelity under mask
writing process variations such as energy fluctuation. It is useful for MPC to switch its correction strategy and permit the
use of advanced mask correction techniques in those local care-areas where they provide maximum wafer benefits. The
use of mask correction techniques tailored to localized post-OPC design can result in similar desired level of data
volume, run time, and write time. ASML Brion and NCS have jointly developed a method to feedforward the care-area
information from Tachyon LMC to NDE-MPC to provide real benefit for improving both mask writing and wafer
printing quality.
This paper explains the detail of OPC care-area feedforwarding to MPC between ASML Brion and NCS, and shows the
results. In addition, improvements on mask and wafer simulations are also shown. The results indicate that the worst
process variation (PV) bands are reduced up to 37% for a 10nm tech node metal case.
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