KEYWORDS: Extreme ultraviolet lithography, Metrology, 3D metrology, Nondestructive evaluation, Line width roughness, Atomic force microscopy, Surface roughness, Photoresist materials, Line edge roughness, Algorithm development
EUV lithography enables continued scaling beyond 5nm nodes and allows the employment of single patterning methods with improved resolution. Thinner photo-resist layers with shrinking feature sizes consequently make stochastic errors worse during the lithography step and require a metrology solution with sub-nanometer resolution and information in the third dimension (depth and full profile shape). Atomic force microscopy (AFM), a topography imaging technique, can achieve the required precision to capture critical dimensions of photoresist patterns in 3 dimensions, but it is generally limited by the ability to fully resolve deep and narrow structures, can be destructive and suffer from low throughput. Here, we show validation of a novel fully automated in-line AFM system, QUADRA, that overcomes these challenges. Details relevant for use in HVM are reported on line and space EUV photoresist patterns after development (ADI).
Pitch scaling of interconnects is required for 3D system integration with the industry shifting to bumpless bonding technology. However, hybrid metal/dielectric bonding requires tight process control of planarity after chemical mechanical polishing (CMP) to avoid bonding voids. Due to its sub-angstrom resolution, atomic force microscopy (AFM) is typically used to assess the nano-topography but conventional systems suffer from increased noise floor at high scanning speeds making it unsuitable for high-volume manufacturing (HVM). Here, we validate a novel in-line high-throughput AFM system (QUADRA) by reporting the topographical parameters of 250 nm and 1 μm size copper nano-pads at high scanning speeds that reach tens of wafers per hour throughput.
Advanced semiconductor nodes are pushing the limits of feature sizes and require metrology with sub-nm resolution without compromising on the throughput as needed for in-line process control. Recently, high-throughput scanning probe microscopy (SPM) based metrology and inspection tools capable of meeting these needs have been introduced to the market and qualified for use in HVM. While innovative measurement methods and tool architecture have allowed for a leap of improvement in throughput, the next step in further reducing imaging time can be obtained through the application of machine learning for enhancing the resolution of measured images for extraction of relevant parameters. In this work, we provide the general framework under which a neural network-based resolution enhancer is designed and used for SPM images. We showcase the effectiveness of this framework using measurements performed on Line/Space structures with a pitch of 200 nm. For the reusability of a pre-developed pre-trained model, we additionally leverage transfer learning and show that a new model for slightly differing structures can be re-trained and calibrated with a smaller data set of measurements performed on Line/Space structures with a pitch of 100 nm.
Process control of advanced semiconductor nodes is not only pushing the limits of metrology equipment requirements in terms of resolution and throughput but also in terms of the richness of data to be extracted to enable engineers to finetune the process steps for increased yield. The move towards 3D structures requires extraction of critical dimension parameters from structures which can vary largely from layer to layer. For in-line process control, the necessary automation forces the development of layer and equipment-specific dedicated image processing algorithms. Similarly, with the increase in stochastic defects in the EUV era, detection of defects at the nm scale requires the identification of features captured in low resolution to meet the throughput requirements of HVM fabs, which can again lead to custom algorithm development. With the emergence of ML-based image processing methods, this process of algorithm development for both cases can be accelerated. In this work, we provide the general framework under which the images obtained from high-speed scanning probe microscopy-based systems can be used to train a network for either feature detection for parameter extraction or defect identification.
High-NA EUV technology enables cost-effective patterning below the 5nm node. The integration is simpler but still requires multiple innovations. Thinner resists are needed for single-patterning enablement. The decrease in thickness poses a challenge for traditional metrology and inspection systems like OCD or CD-SEM, which lose sensitivity due to diminishing interaction volume. The reverse is true for Scanning Probe Microscopy, which excels in the low-height patterning regime. Here we discuss patterning metrology and introduce defect inspection / review applications for High-NA EUV patterning using a high-throughput SPM.
Improved resolution of the High-NA EUV technology comes with thinner photoresist and smaller aspect-ratio requirements. Trade-offs include more stringent process control needs for resist loss and line roughness. Traditional metrologies like OCD or CD-SEM lose sensitivity due to diminishing interaction volume. A metrology technique that thrives in this regime is Scanning Probe Microscopy: thinner resist allows for higher scanning speed, and smaller aspect ratio for higher measurement accuracy. Here we propose a High-Throughput SPM technique as key enabler for High-NA EUV process control. Detailed, high-density full wafer measurements of resist loss, CD and roughness are enabled by a high-throughput, 4-head SPM toolset, and compared for different resist thicknesses down to 10nm. Sampling schemes consistent with scanner throughput are considered.
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