Metal containing resists (MCR) are one of the candidates for extreme ultraviolet resists aiming to achieve the resolution, linewidth roughness, and sensitivity requirements of advanced design nodes. MCRs intrinsically have high etch resistance owing to their metal content. Therefore, low resist thickness (∼18 nm) is sufficient to transfer resist patterns into an underlying hard mask. Also, the thin resist reduces susceptibility to pattern collapse during development because of low aspect ratio. However, thus far, little attention has been paid to optical metrology and inspectability (overlay, defect inspection, scatterometry, etc.) of these resists, which is another critical requirement to move MCR toward high-volume manufacturing. We investigate the overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR), it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.
In this paper, we investigate overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR) it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.
The recent developments in scanner technology improved the ability to control intra-field overlay at high-order across the exposure field. However, this is still in several millimeter lateral resolution control ability at its best, leaving residual errors in the sub-millimeter to few millimeter regime without the ability to further suppress them to the target specification, nevertheless, not to the sub-nanometer magnitude.
In this work, we have empirically evaluated the ZEISS state-of-the-art mask tuning solution named ForTune ERC (Enhanced Registration Control). This solution is based on laser processing of the mask bulk by the ZEISS ForTune tool. It allows to suppress few nanometer overlay residuals (post the scanner best-can-do) down to deep sub-nanometer, all even at sub-millimeter sampling resolution (x1 wafer level) and low-to-high residuals modulating frequency.
For the sake of this study, we have used a dual-image mask to form one overlay signature at wafer side. Two wafers have been exposed prior to the laser-based tuning of the mask bulk; the wafers overlay error was measured and used as an initial overlay problem to begin with. A second exposure of two additional wafers was performed post the problem-solving by the ERC model and the consequent mask laser-based tuning. The pre/post wafers were then compared to examine the improvement in overlay at wafer side. CD uniformity (CDU) data has been collected as well, to confirm no degradation in CDU due to the ForTune ERC process.
The combination of this advanced method of intra-field control with high-order correction per exposure (CPE) by the scanner, provides an efficient co-optimized solution to tightly control the overlay of existing and future nodes at DUV litho.
In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.
ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci).
The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.
Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.
In this paper, we propose a new generation of software platform and development infrastructure which can integrate specific metrology business modules. For example, we will show the integration of a chemistry module dedicated to electronics materials like Direct Self Assembly features. We will show a new generation of image analysis algorithms which are able to manage at the same time defect rates, images classifications, CD and roughness measurements with high throughput performances in order to be compatible with HVM. In a second part, we will assess the reliability, the customization of algorithm and the software platform capabilities to follow new specific semiconductor metrology software requirements: flexibility, robustness, high throughput and scalability. Finally, we will demonstrate how such environment has allowed a drastic reduction of data analysis cycle time.
This paper will demonstrate the complementary RegC® and TWINSCANTM solution for improving the OPO by cooptimizing the correction capabilities of the individual tools, respectively. As a consequence, the systematic intra-field fingerprints can be decreased along with the overlay (OVL) error at wafer level. Furthermore, the application could be utilized for extending some of the scanner actuators ranges by inducing a pre-determined signatures. These solutions perfectly fit into the ASML Litho InSight (LIS) product in which feedforward and feedback corrections based on YieldStar overlay and other measurements are used to improve the OPO. While the TWINSCANTM scanner corrects for global distortions (up to third order) - scanner Correctable Errors ( CE), the RegC® application can correct for the None Correctable Errors (NCE) by making the high frequency NCE into a CE with low frequency nature. The RegC® induces predictable deformation elements inside the quartz (Qz) material of the reticle, and by doing so it can induce a desired pre-defined signature into the reticle. The deformation introduced by the RegC® is optimized for the actual wafer print taking into account the scale and ortho compensation by the scanner, to correct for the systematic fingerprints and the wafer overlay. These two applications might be very powerful and could contribute to achieve a better OPO performance.
In the frame of the development of a triple patterning BEOL scheme of 10 nm node layer, we compare IBO targets (standard AIM, AIMid and multilayer AIMid). The metrology tools used for the study are KLA-Tencor’s nextgeneration Archer 500 system (scatterometry- and imaging-based measurement technologies on the same tool).
The overlay response and fingerprint of these targets will be compared using a very dense sampling (up to 51 pts per field). The benefit of indie measurements compared to the traditional scribes is discussed. The contribution of process effects to overlay values are compared to the contribution of the performance of the target. Different targets are combined in one measurement set to benefit from their different strengths (performance vs size).
The results are summarized and possible strategies for a triple patterning schemes are proposed.
We will show that these reference data can be used to validate the DBO overlay results (correctables and residual fingerprints).
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