We have used large-field-of-view voltage contrast metrology to determine the design rules on a pitch 28 nm single-exposure extreme ultra violet dual damascene process, and to study a use case in which two design parameters, metal tip-to-tip critical dimension and via-to-line placement, interact nontrivially in the yield determination. By designing proper test structures, it is possible to determine the different failure mechanisms for the given process integration and determine the patterning cliffs and design rules.
Image contrast is an important measure of image quality, especially for EUV lithography where high contrast can mitigate stochastic process fluctuations1 such as Line-Edge Roughness (LER), Line Width Roughness (LWR), Local CD Uniformity (LCDU) and stochastic defects. In this paper, several aspects of image contrast for EUV lithography are discussed. We will look at some of the fundamental mechanisms which degrade image contrast, including resist blur from acid diffusion. We assume the imaging of dense line/space images with k1<0.5. This assumption guarantees that the image is a simple sinusoid, and implies that the exposure latitude is proportional to the image contrast. We then consider various methods to experimentally measure image contrast. The classic measure would be to measure the exposure latitude from a Focus/Exposure Matrix (FEM) wafer. The exposure latitude is generally giving a contrast measure which is averaged over some portion of the wafer. In this paper, we propose the use of MEEF (Mask Error Enhancement Factor) targets to track contrast at specific locations on the wafer. In principle, one could measure many points across the image field (or even across the whole wafer) to map out the spatial variation of contrast, i.e. a contrast map. The paper includes experimental contrast measurements that relate to stage fading, source shape and resist blur from different processes. We will also briefly look at fading from the Pole-to-Pole image shift, and how to mitigate this with a novel exposure method called Dual Monopole.
In this work we studied the impact of stochastic resist defects on electrical measurements of BEOL structures, and seek to demonstrate that large electrical test structures, built with a relatively simple patterning flow, can be used in the early stages of resist, and patterning development, as the electrical failures are almost exclusively caused by resist defects. To that end, single-layer electrically testable metal patterns at minimum metal pitch of 28nm were created using a single 0.33NA-EUV exposure and a metal damascene process flow. A bright field mask was exposed with a metal-organic, negative-tonedevelopment resist process to create trench structures that are transferred into an oxide dielectric layer. Following this, the trenches were filled with ruthenium (Ru) for electrical testing of meander resistor and fork-fork structures.
EUV resists, while improving steadily, generate a number of nanobridge or break defects that increases quickly as the pitch approaches 30 nm. Inline inspection methods are therefore needed to reliably detect patterning defects smaller than 20 nm. Massive e-beam metrology provides the high resolution needed to measure these defects, while remaining compatible with HVM throughput requirements. In this work, we used a direct metal (Ru) etch process, to fabricate EUV-patterned electrical structures in the 32 nm-36 nm pitch range. We demonstrate an almost one-to-one correspondence between the e-beam metrology yield of the structures, and their electrical yield. The e-beam inspection is realized with a large-field-of-view HMI eP5 e-beam system. The match between e-beam and electrical yield shows that our e-beam inspection is able to catch all electrically relevant line breaks, while excluding false flags. These results demonstrate the capability of massive e-beam inspection in predicting electrical yield.
Extreme ultraviolet (EUV) lithography is the technology for high volume manufacturing (HVM) of semiconductor ICs for photoresist patterns smaller than 75nm pitch¹. A persistent challenge of the EUV scanner is to supply a high contrast image with enough photons to the photoresist (PR) to meet HVM productivity targets with acceptable dimensional and defectivity control. Local stochastic variability in dimension and placement dominates the total dimension control budget and reducing that variability by increasing the exposure dose comes at the cost of scanner throughput. Our objective is to deliver holistic patterning solutions by co-optimization of patterning film stack, lithography, and subsequent etch processes to transfer the patterns to the target layer with CD and placement control of order 1nm or less! This synergistic approach enables circuit fabrication customers to manage the tradeoff between stochastic defects and productivity in EUV patterning.
Enhanced EUV lithography (EUVL) resist performance, combined with optimized post processing techniques, are vital to ensure continued scaling and meet the requirements for the industry N5 node and beyond. Sequential infiltration synthesis (SIS) is a post lithography technique that has the potential to significantly improve the EUVL patterning process for stochastic nano-failures and line roughness, both major topics in EUV lithography research. SIS is an ALD-like technique that infiltrates polymeric photoresists, forming a metal framework using the lithography pattern as a template. Hardening of the photoresist improves the pattern quality and gives more flexibility to subsequent pattern transfer steps. We have evaluated the performance of SIS for an EUV Chemically Amplified Resist (CAR) platform printing 32 nm pitch line/space patterns and ultimately structures that are representative of standard semiconductor manufacturing. A combined lithography-SIS-etch process and a standard lithography-etch process were optimized for an industry relevant stack with pattern transfer into a TiN layer. This allows for the first time a justified comparison between a EUVL-SIS and a standard EUVL patterning process, showing the benefits of SIS regarding roughness, exposure latitude and nano-failure mitigation. Power Spectral Density (PSD) analysis accurately demonstrates and explains the type of roughness improvement. Nano-failure analysis is done by measuring large areas at different exposure doses and shows the improvement of the nano-failure free window when applying a EUVL-SIS patterning process. We conclude by examining to which extent combining the best lithography process with an optimized SIS step will lead to a better roughness and nano-failure performance, essential to meeting industry requirements.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.