The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.
We present a simple method of deep anisotropic etching of silicon up to 400 μm with nearly vertical sidewall profile for thermopile devices. The method is based on the time-multiplexed etching which is a modified case of the Bosch deep reactive ion etching process. This process is mainly adjusted by chuck power and it is divided into three steps which are zero bias deposition step, high bias polymer removing step, and low bias silicon etching step. Compared with the standard Bosch process, this modified strategy shows advantage of etch rate and selectivity.
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