Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH4/NH3/N2. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager fneu value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.
The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.