Modern Integrated Circuits (IC) manufacturing consists of a complex series of process steps and each transition to smaller semiconductor technology nodes has come with a significant increase in the number of steps. Apart from this increased technological complexity, also the cost of semiconductor manufacturing has risen significantly. A high yield is therefore of utmost importance to ensure the overall profitability of the modern IC manufacturing process, meaning that each process step needs to be executed flawlessly, in particular due to accumulative nature of yield loss.
Photolithography is one of the many process steps in IC manufacturing that is executed repeatedly and overlay is one of its most critical parameters. Maintaining good overlay performance is thus key for maximizing yield and guaranteeing the overall profitability of the IC production process. Overlay metrology plays an important role in keeping this good performance in high-volume manufacturing (HVM), and the measurements are used as input for the Advanced Process Control (APC) system as well as for lot dispositioning. Preferably, the amount of metrology is reduced to a bare minimum to reduce cost and decrease fab cycle time, and overlay is typically measured on only a fraction of the wafers. In case metrology reduction is going too far, then there is a risk that bad wafers and/or lots pass, resulting in potential yield loss or even wafer scrap, which will increase the cost again. The challenge is to find the sweet spot for using the available metrology in the most efficient way.
Virtual metrology is a solution that aims to enable metrology coverage for every single wafer, and with that applications like smarter sampling with the goal of using metrology more efficiently. Basically, virtual metrology is the use of algorithms to predict wafer properties like overlay based on previous metrology measurements and/or processing equipment sensor data. In previous work, we developed virtual metrology, or computational overlay, based on a hybrid approach that combines domain knowledge-based physical modeling with machine learning. A good prediction performance was demonstrated on the critical overlay between contact and gate layers that were exposed with chuck dedication. Furthermore, we also showed that computational overlay could be used to reduce the field magnification errors that were observed in the lot-to-lot variation.
In this paper, we build upon our earlier work and extend the applicability of the computational overlay model towards layers that are exposed without chuck dedication, or even on different scanners. We will assess the prediction performance on a few Via layers in the back-end-of-line. Furthermore, as the model is able to predict the overlay for all wafers in the lot, we will demonstrate its capability of detecting an intermittent first wafer effect on one particular lithography cluster that was causing non-optimal quality.
