Mr. Jean De-Caunes Profile

Jean De-Caunes

at STMicroelectronics

SPIE Involvement:

Author

Publications (10)

Proceedings Article | 26 March 2019 Presentation + Paper

New approach for APC and measurement sampler interaction in a complex process mix logic fab

L. Lecarpentier, A. Mili, J. Decaunes, B. Le Gratiet

Proceedings Volume 10959, 109591Q (2019) https://doi.org/10.1117/12.2514943

KEYWORDS: Metrology, Overlay metrology, Semiconducting wafers, Process control, Reticles, Lithography, Logic, Photomasks, Process engineering, Scanners

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Since the beginning of the Crolles 300mm fab, more and more complex logic technologies, down to 28nm node, have been developed. At the same time, the products mix increased at a very high level : Specifically for the lithography area, this complexity leads to an intricate management of thousands of masks, hundreds of track process recipes, used on various lithography clusters types (193nm including immersion, 248nm and 365nm). In order to apply the best process parameters, APC software is used since many years, and was continuously improved. It now takes into account multi-variate parameters coming from various process contexts. A new sampling tool was developed to adjust the measurements control plan. All kind of in-line measures are addressed (thickness, critical dimensions, overlay…). Since the beginning of this software development, the approach was to keep in mind the APC model. The objective was to use the APC data’s (alarms and warnings) to secure the sampling decisions without compromising the regulation loops stability.

This sampling tool can use different inputs (production, tools, APC…) in a dynamic way. This means that the system is dynamic for both process and metrology aspects, and can be adapted to integrate different variables and external events. A real time communication flow was created between APC and sampling tool. Even if the measurement skip decision is taken by the sampling tool, the APC feedback is systematically requested when run to run is involved, like for all lithography process steps. The strength is to deal with high products / mix complexity and react in real time to new product introduction, process deviation, atypical lots including R&D projects and sudden change of the products mix. Both tools are so linked that the sampler remains invisible. Process engineers continue to manage and control lithography process through APC tool mainly.

In parallel, different alarms and triggers have been implemented, including a specific “crisis” mode to quickly respond to the metrology equipment loading or availability variability.

The sampler introduction allowed an optimization of the metrology toolset costs and lot cycle time improvement. Also as a consequence, a more efficient metrology control plan, with an optimized balance between process criticality and metrology requirements.

Future opportunities are related to more dynamic behaviors, as a dynamic sampling rate adapted to metrology capacity, function of the real time metrology capacity or sampling decision dynamically based on process variability components.

Proceedings Article | 13 March 2018 Presentation + Paper

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

Benjamin Duclaux, Jean De Caunes, Robin Perrier, Maxime Gatefait, Bertrand Le Gratiet, Jean-Damien Chapon, Cédric Monget

Proceedings Volume 10585, 105851C (2018) https://doi.org/10.1117/12.2292446

KEYWORDS: Overlay metrology, Optical alignment, Scanners, Process control, Data modeling, Reticles, Reliability, Optical lithography

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Proceedings Article | 4 September 2015 Paper

AGILE integration into APC for high mix logic fab

M. Gatefait, A. Lam, B. Le Gratiet, M. Mikolajczak, V. Morin, N. Chojnowski, Z. Kocsis, I. Smith, J. Decaunes, A. Ostrovsky, C. Monget

Proceedings Volume 9661, 96610P (2015) https://doi.org/10.1117/12.2194746

KEYWORDS: Sensors, Metrology, Semiconducting wafers, Logic, Data processing, Metals, Wafer-level optics, Optical properties, Photomasks, Scanners

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For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

SPIE Journal Paper | 10 April 2015

Patterning critical dimension control for advanced logic nodes

Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud

JM3, Vol. 14, Issue 02, 021103, (April 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.2.021103

KEYWORDS: Semiconducting wafers, Optical lithography, Critical dimension metrology, Process control, Photomasks, Etching, Logic, Metrology, Lithography, Optical proximity correction

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Proceedings Article | 17 October 2014 Paper

How holistic process control translates into high mix logic fab APC?

B. Le-Gratiet, M. Gatefait, J. Ducotè, J. Decaunes, A. Lam, B. Beraud, M. Mikolajczak, A. Pelletier, B. Orlando, F. Sundermann, A. Ostrovsky, C. Lapeyre

Proceedings Volume 9231, 92310V (2014) https://doi.org/10.1117/12.2064795

KEYWORDS: Semiconducting wafers, Photomasks, Process control, Scanners, Metrology, Etching, Databases, Logic, Data modeling, Control systems

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Proceedings Article | 10 April 2013 Paper

Overlay improvement through lot-based feed-forward: applications to various 28nm node lithography operations

B. Orlando, M. Gatefait, J. De-Caunes, P.J. Goirand

Proceedings Volume 8681, 868117 (2013) https://doi.org/10.1117/12.2011117

KEYWORDS: Lithography, Overlay metrology, 193nm lithography, Semiconducting wafers, Double patterning technology, Optical alignment, Optical lithography, Scanners, Remote sensing, Control systems

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Proceedings Article | 5 April 2012 Paper

Integration and automation of DoseMapper in a logic fab APC system: application for 45/40/28nm node

Bertrand Le Gratiet, Christophe Salagnon, Jean de Caunes, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Jean Massin, Alice Pelletier, Joel Metz, Yoann Blancquaert, Regis Bouyssou, Arthur Pelissier, Olivier Belmont, Anne Strapazzon, Anna Phillips, Thierry Devoivre, Emilie Bernard, Estelle Batail, Lionel Thevenon, Benedicte Bry, Fabrice Bernard-Granger, Ahmed Oumina, Marie-Pierre Baron, Didier Gueze

Proceedings Volume 8324, 83241Y (2012) https://doi.org/10.1117/12.911882

KEYWORDS: Etching, Photomasks, Logic, Databases, Control systems, Scanners, Metrology, Semiconducting wafers, Lithography, Process control

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Proceedings Article | 2 April 2010 Paper

Overlay breakdown methodology on immersion scanner

Auguste Lam, Francois Pasqualini, Jean de Caunes, Maxime Gatefait

Proceedings Volume 7638, 76383L (2010) https://doi.org/10.1117/12.849245

KEYWORDS: Semiconducting wafers, Overlay metrology, Scanners, Data mining, Optical alignment, Metrology, Reticles, Distance measurement, Data modeling, Process modeling

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Proceedings Article | 22 March 2008 Paper

Process control for 45 nm CMOS logic gate patterning

Bertrand Le Gratiet, Pascal Gouraud, Enrique Aparicio, Laurene Babaud, Karen Dabertrand, Mathieu Touchet, Stephanie Kremer, Catherine Chaton, Franck Foussadier, Frank Sundermann, Jean Massin, Jean-Damien Chapon, Maxime Gatefait, Blandine Minghetti, Jean de-Caunes, Daniel Boutin

Proceedings Volume 6922, 69220Z (2008) https://doi.org/10.1117/12.776889

KEYWORDS: Semiconducting wafers, Etching, Critical dimension metrology, Optical lithography, Scatterometry, Reticles, Scanners, Photomasks, Process control, Immersion lithography

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Proceedings Article | 14 March 2006 Paper

Design and use of multivariate approach error analysis APC system

Jean de Caunes, Joost van Herk, Scott Warrick, Bertrand Le Gratiet, Marc Mikolajczak, Jean-Damien Chapon, Cedric Monget, Jan-Willem Gemmink

Proceedings Volume 6155, 615507 (2006) https://doi.org/10.1117/12.657177

KEYWORDS: Reticles, Critical dimension metrology, Semiconducting wafers, Process modeling, Overlay metrology, Oxides, Metrology, Error analysis, Semiconductors, Scanners

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