Mr. Chao Zhang Profile

Chao Zhang

at Adaps Photonics

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Publications (2)

Proceedings Article | 8 March 2024 Presentation + Paper

Piccolo gated: a CMOS 32x32 SPAD camera with all-solid-state nanosecond time gating and PCIe readout for single-photon time-domain DCS and near-infrared optical tomography

Paul Mos, Scott Lindner, Chao Zhang, Michael Wayne, Tommaso Milanese, Claudio Bruschini, Edoardo Charbon

Proceedings Volume 12895, 1289507 (2024) https://doi.org/10.1117/12.2692934

KEYWORDS: Single photon avalanche diodes, Field programmable gate arrays, Quantum sensors, Time correlated single photon counting, Sensors, Optical tomography, Quantum correlations, Picosecond phenomena, Signal detection, Quantum gates

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The Piccolo gated sensor features a 32x32 SPAD array of single-photon avalanche diodes (SPADs) operating in time-correlated single-photon counting (TCSPC). The chip enables event-driven readout and a maximum count rate of 220 Mcps. The sensor is based on the original Piccolo architecture, whereas the pixel was redesigned to accommodate a sub-nanosecond time gating circuitry. As a result, the pitch was increased by 3 μm to 31 μm with a slightly lower fill factor of 23.7%. The time-gating circuitry comprises active recharge to activate the gate and a fast switch to de-activate the SPAD. The sensor is equipped with 128 dynamically allocated, 50 ps time-to-digital converters (TDCs) at the bottom of the array. Four TDCs are shared among 32 SPADs in each column, where a mechanism of reallocation is used to optimize the use of TDCs and to minimize photon loss. Time gating can reduce both uncorrelated and correlated noise by reducing overall active time and by increasing relaxation time after detection, respectively. Upon acquisition of TCSPC data, the FPGA reorganizes it in histograms, which may be dynamically allocated and reduced in the number of bins to optimize memory use and data transfer from the FPGA to an external Mac/PC. The TDCs may also be calibrated to suppress differential and integral nonlinearities on-FPGA. Timestamps are stored in DDR3 and streamed out of the FPGA through PCIe with a data rate of 5.12 Gbps. Thanks to these techniques, the maximum count rate of the sensor was increased by about 3×. The time gating feature was implemented to extend dynamic range, and therefore depth, of near-infrared optical tomography (NIROT) and g(2) multi-depth time-domain diffuse correlation spectroscopy (TD-mDCS). Time gating is especially useful in NIROT and mDCS, as it helps suppress large numbers of early photons reflected back from the sample’s surface, e.g. the skull or skin. Thus, the Piccolo-gated architecture could show its suitability in these imaging modality.

Proceedings Article | 20 February 2017 Paper

Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

C. Zhang, V. T. S. Dao, T. Etoh, E. Charbon

Proceedings Volume 10328, 1032807 (2017) https://doi.org/10.1117/12.2268877

KEYWORDS: 3D image processing, Image sensors, Imaging arrays, Oscillators, Clocks, Sensors, Mirrors, Oscilloscopes, Photons, Imaging systems

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