Mr. Takamitsu Komaki Profile

Takamitsu Komaki

at Canon Inc

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Publications (4)

Proceedings Article | 23 March 2020 Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Atsushi Kimura, Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Keita Sakai, Hiroshi Morohoshi, Toshiya Asano, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 11324, 113240B (2020) https://doi.org/10.1117/12.2551985

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Optical alignment, Photomasks, Distortion, Overlay metrology, Optical lithography, Wafer testing, Lithography, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results. On test wafers, XMMO of 3.2nm and 2.8nm in x and y respectively was demonstrated. There is also an opportunity to further improve results by applying wafer chucks with better flatness specifications. Further advances have also been made through the application of a multi-wavelength alignment strategy. Finally, we discuss how computational methods can enhance NIL productivity and reduce the number of learning cycles

Proceedings Article | 23 March 2020 Presentation + Paper

Through-the-mask (TTM) optical alignment for high volume manufacturing nanoimprint lithography systems

Takamitsu Komaki, Yasuyuki Unno, Takahiro Matsumoto, Toshiki Iwai, Nozomu Hayashi, Tomokazu Taki, Tohru Kawashima, Satoshi Iino, Shinichirou Hirai, Ken Minoda, Takafumi Miyaharu, Kazuhiro Takahashi, Kazuhiko Mishima

Proceedings Volume 11327, 113270Y (2020) https://doi.org/10.1117/12.2551980

KEYWORDS: Optical alignment, Semiconducting wafers, Photomasks, Nanoimprint lithography, Overlay metrology, Error analysis, Wafer testing, Diffraction, High volume manufacturing, Distortion

Read Abstract +

Proceedings Article | 27 June 2019 Paper

Status of overlay performance for NIL high volume manufacturing

Tatsuya Hayashi, Yukio Takabayashi, Mitsuru Hiura, Takehiko Iwanaga, Hiroshi Morohoshi, Takamitsu Komaki

Proceedings Volume 11178, 111780J (2019) https://doi.org/10.1117/12.2536315

KEYWORDS: Semiconducting wafers, Distortion, Nanoimprint lithography, Overlay metrology, Photomasks, Wafer testing, Optical alignment, Source mask optimization, Lithography, Optical lithography

Read Abstract +

Nanoimprint lithography (NIL) techniques are known to possess replication resolution below 5nm. A specific form of imprint lithography using jetted resist has been developed for manufacturing advanced CMOS memory. Canon’s NIL process involves field-by-field inkjet deposition of a low viscosity resist fluid followed by imprinting with nano-scale precision overlay. A mask with a relief structure is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is separated from the substrate leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. The linear response of the HODC system was demonstrated for multiple high order terms and on test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was achieved. Additionally an SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications.

Proceedings Article | 26 March 2019 Presentation + Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Hiroshi Morohoshi, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 10958, 109580B (2019) https://doi.org/10.1117/12.2514924

KEYWORDS: Semiconducting wafers, Optical alignment, Wafer testing, Nanoimprint lithography, Distortion, Overlay metrology, Photomasks, Source mask optimization, Optical lithography, Lithography

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. On test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was demonstrated. SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications. Comparable results were also achieved on device wafers by applying a multi-wavelength alignment strategy and a feed forward strategy to realize align signal convergence within the allocated 0.60 second budget.

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