Dr. Suresh Lakkapragada Profile

Dr. Suresh Lakkapragada

Self Employed at KLA Corp

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Publications (10)

Proceedings Article | 20 November 2024 Presentation + Paper

Enhancing fab yield with the high-reliability automation application Reticle Analyzer (RA)

Olivier Fagart, Laurent Lecarpentier, Dongmei Wu, Suresh Lakkapragada, Changqing Hu, Yuehui Wang, Li Xie, Derui Li, Jing Jiao, Zeyu Lei, Marco Polli, Vikram Tolani

Proceedings Volume 13216, 1321613 (2024) https://doi.org/10.1117/12.3034265

KEYWORDS: Analog to digital converters, Reticles, Printing, Inspection, Semiconducting wafers, Critical dimension metrology, Air contamination, Lithography, Optical proximity correction, Manufacturing

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In advanced manufacturing fabs, mask inspection plays a pivotal role in securing the mask quality and wafer yield. A single defect on a mask can potentially impact thousands of wafers, underscoring the criticality of accurate defect disposition. While operators can confidently classify approximately 90% of defects manually, the remaining 10% are often misclassified, directly affecting production yield. As technology nodes shrink, the adoption of advanced techniques such as Optical Proximity Correction (OPC) and Sub-Resolution Assist Feature (SRAF) in mask manufacturing poses additional challenges for operators in determining defect dispositions. Additionally, the time-consuming online defect review process hampers production efficiency. To address these challenges, STMicroelectronics has adopted an intelligent reticle disposition system known as Reticle Analyzer^TM (RA). RA integrates three essential applications. First, Automated Defect Classification (ADC) ensures precise defect classification, minimizing misclassifications. By leveraging defect type, topology, and severity as outputted from advanced image processing algorithms, ADC significantly improves defect classification accuracy. Second, Defect Progressing Monitor (DPM) continuously monitors defect behavior over time. It alerts operators when defects deteriorate, enabling timely intervention to prevent yield loss. Additionally, DPM provides information on the total defect count per mask based on inspection time, allowing for early haze detection and monitoring. Third, Lithography Printability Review (LPR) assesses the potential impact of defects based on lithographic printability predictions. It simulates the aerial image on the wafer and provides comprehensive analytics to assist operators in evaluating the risks of printing. In this paper, we present the workflow of ADC, LPR, and DPM products. We discuss the qualification process during production and highlight typical production cases that showcase the advantages of RA adoption. RA’s deployment has proven invaluable in mitigating yield loss, demonstrating its indispensable role in STMicroelectronics fabs.

Proceedings Article | 13 November 2024 Presentation

Extending EUV mask inspection capability utilizing DUV light: defect capture sensitivity and throughput

Charlie Wu, Adrian Li, Rachel Liu, Lifang Zhang, Zeyu Lei, Suresh Lakkapragada, Amo Chen, Vikram Tonali, Dongxue Chen, Mingwei Li, Shang-Chieh Chien, Ji-Rong Huang, Yi-Wun Wang, Hank Yeh, Yen-Hsun Chen, ShinAn Ku, Shu-Hsien Wu, L. Chen, Chin-Kun Wang

Proceedings Volume 13216, 132161P (2024) https://doi.org/10.1117/12.3053686

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Proceedings Article | 5 October 2016 Paper

Reticle decision center: a novel applications platform for enhancing reticle yield and productivity at 10nm technology and beyond

George Hwa, Raj Bugata, Kaiming Chiang, Suresh Lakkapragada, Vikram Tolani, Sandhya Gopalakrishnan, Chun-Jen Chen, Chin-Ting Yang, Sheng-Chang Hsu, Laurent Tuo

Proceedings Volume 9985, 99851Z (2016) https://doi.org/10.1117/12.2241482

KEYWORDS: Photomasks, Reticles, Inspection, Metrology, Defect inspection, Manufacturing, Semiconducting wafers, Databases, Computing systems, Operating systems

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In the semiconductor IC manufacturing industry, challenges associated with producing defect-free photomasks have been dramatically increasing. At the 10nm technology node, since the 193nm immersion scanner numerical aperture has remained the same 1.35 as in previous nodes, more multi-patterning and aggressive SMO illumination sources are being used to effectively print smaller feature CDs and pitches. To accommodate such specialized sources, more model-based mask OPC and ILT have been used making mask designs very complicated. This in turn makes mask manufacturing very challenging especially for the defect inspection, repair, and metrology processes that need to guarantee defect-free masks. Over the past few years, considerable innovation have been made in the areas of defect inspection and disposition that has ensured continued predictability of mask quality to wafer and final chip yields. The accurate disposition of each mask defect before and after repair has been facilitated by a suite of automated applications such as ADC, LPR, RPG, AIA, etc. that work together with the inspection, repair, and metrology tools and effectively also provide the best possible utilization of the tool capability, capacity and operator resources. In this paper we introduce a new consolidated applications platform called the Reticle Decision Center (RDC) which hosts all these supporting software applications on a centralized server with direct connectivity to mask inspection, repair, metrology tools and more. The paper details how the RDC server is architected to host any application in its native operating system environment and provides for high availability with automatic failover and redundancy. The server along with its host of applications has been tightly integrated with KLA-Tencor’s Teron mask inspectors. The paper concludes with showing benefits realized in mask cycle-time and yield as a result of implementing RDC into a high-volume 10nm mask-shop production line.

Proceedings Article | 1 October 2013 Paper

Improve mask inspection capacity with Automatic Defect Classification (ADC)

Crystal Wang, Steven Ho, Eric Guo, Kechang Wang, Suresh Lakkapragada, Jiao Yu, Peter Hu, Vikram Tolani, Linyong Pang

Proceedings Volume 8880, 88800C (2013) https://doi.org/10.1117/12.2030844

KEYWORDS: Inspection, Photomasks, Defect inspection, Defect detection, Classification systems, Image classification, Image resolution, Manufacturing, Resolution enhancement technologies, SRAF

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As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The adoption of RET techniques like aggressive OPC, sub-resolution assist features combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for mask inspection operators and engineers. Therefore a comprehensive approach is required in handling defects post-inspections by correctly identifying and classifying the real killer defects impacting the printability on wafer, and ignoring nuisance defect and false defects caused by inspection systems. This paper focuses on the results from the evaluation of Automatic Defect Classification (ADC) product at the SMIC mask shop for the 40nm technology node. Traditionally, each defect is manually examined and classified by the inspection operator based on a set of predefined rules and human judgment. At SMIC mask shop due to the significant total number of detected defects, manual classification is not cost-effective due to increased inspection cycle time, resulting in constrained mask inspection capacity, since the review has to be performed while the mask stays on the inspection system. Luminescent Technologies Automated Defect Classification (ADC) product offers a complete and systematic approach for defect disposition and classification offline, resulting in improved utilization of the current mask inspection capability. Based on results from implementation of ADC in SMIC mask production flow, there was around 20% improvement in the inspection capacity compared to the traditional flow. This approach of computationally reviewing defects post mask-inspection ensures no yield loss by qualifying reticles without the errors associated with operator mis-classification or human error. The ADC engine retrieves the high resolution inspection images and uses a decision-tree flow to classify a given defect. Some identification mechanisms adopted by ADC to characterize defects include defect color in transmitted and reflected images, as well as background pattern criticality based on pattern topology. The final classification uses a matrix decision approach for achieving the final defect disposition. As a first step for qualifying ADC for high volume production, the defect classification results obtained with ADC are compared to the operator classification. Matching rates of greater than 90% were achieved when compared to operator defect classifications. Moreover, no critical defect has been missed. ADC performance was proven to be qualified for deployment in full volume mask manufacturing production flow.

Proceedings Article | 20 September 2013 Paper

Automated Defect Classification (ADC) and Progression Monitoring (DPM) in wafer fab reticle requalification

T. Yen, Rick Lai, Laurent Tuo, Vikram Tolani, Dongxue Chen, Peter Hu, Jiao Yu, George Hwa, Yan Zheng, Suresh Lakkapragada, Kechang Wang, Danping Peng, Bill Wang, Kaiming Chiang

Proceedings Volume 8880, 88800A (2013) https://doi.org/10.1117/12.2031786

KEYWORDS: Inspection, Reticles, Photomasks, Semiconducting wafers, Contamination, Air contamination, Optical proximity correction, Scanners, Defect inspection, Visualization

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Proceedings Article | 8 November 2012 Paper

Computational defect review for wafer-fab reticle requal, part 1: mask plane inspections

Vikram Tolani, Grace Dai, Suresh Lakkapragada, Peter Hu, Kechang Wang, Lin He, Ying Li, Danping Peng, George Hwa, Linyong Pang

Proceedings Volume 8522, 85221O (2012) https://doi.org/10.1117/12.977138

KEYWORDS: Inspection, Reticles, Photomasks, Semiconducting wafers, Image processing, Air contamination, Resolution enhancement technologies, Defect detection, Image restoration, Scanners

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Proceedings Article | 24 March 2006 Paper

Improved profile measurement accuracy via feed-forward spectroscopic ellipsometry

Robert Peters, Suresh Lakkapragada

Proceedings Volume 6152, 61522I (2006) https://doi.org/10.1117/12.656447

KEYWORDS: Critical dimension metrology, Atomic force microscopy, Spectroscopic ellipsometry, Metrology, Lithography, Photoresist materials, Signal processing, Photomasks, Optics manufacturing, Optical testing

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In recent years, optical metrology methods, based on spectroscopic ellipsometry (SE), have gained a strong foothold for use in measuring the 2-dimensional profiles of integrated device features. While optical methods generally provide superior metrology performance compared to other metrology methods, there still remain some challenges to meet precision and accuracy requirements as integrated device geometries continue to shrink at an aggressive rate. Process engineers are employing several new techniques in order to meet device patterning requirements while maintaining manufacturing-worthy process windows. These techniques include thinning the photoresist layers and adding additional underlayer films to act as hard masks for subsequent pattern transfer steps. Thinning the photoresist layer reduces the aspect ratio of patterned grating targets, which, in turn, reduces the signal-to-noise (S/N) ratio of the optical profile measurement. The additional films in the process stack below the gratings increase the number of optical interfaces that must be taken into account when building the optical model for the measurement. The increased complexity of the optical model increases the likelihood that there will be cross-correlation between the underlying films and the grating profile parameters (Critical Dimension or CD, Height, and Sidewall Angle or SWA). The reduction in S/N and increase in cross-correlation often have negative impacts on the precision and overall accuracy of the reported values for the grating profile parameters. In this paper, we will discuss a methodology to overcome the issues described above. The methodology involves performing a standard SE film thickness measurement on an open pad area in close proximity to the grating target of interest. The thickness values are then fed forward to a subsequent SE measurement of the grating target. With the underlayer thickness values fixed based on the film thickness measurement, only the grating profile parameters are solved for during the grating measurement. Decoupling the underlayer film measurement from the grating measurement, greatly reduces, and even eliminates cross-correlation between parameters. Both SE measurements are completed with a total move-acquire-measurement (MAM) time that is <10 seconds per pair, and the resulting values reported for CD, Height, and SWA are more accurate when compared to reference metrology such as Atomic Force Microscopy (AFM). Supporting data will be presented from measurements taken on a 65nm technology node gate lithography process. Using the feed-forward process, the correlation and slope of profile parameters measured via SE compared to AFM measurements is greatly improved. Furthermore, systematic anti-correlation between resist height and SWA that was observed during simultaneous measurement of the film stack and grating is eliminated when the film measurement is decoupled and fed-forward into the grating measurement.

Proceedings Article | 2 June 2003 Paper

Improved gate process control at the 130-nm node using spectroscopic-ellipsometry-based profile metrology

J. Scott Hodges, Yu-Lun Lin, Dale Burrows, Ray Chiao, Robert Peters, Srinivasan Rangarajan, Kamal Bhatia, Suresh Lakkapragada

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485002

KEYWORDS: Etching, Metrology, Critical dimension metrology, Transistors, Spectroscopic ellipsometry, Process control, Semiconducting wafers, Oxides, Control systems, Semiconductors

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The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps, to back-end-of-line device parametric test results, enables semiconductor manufacturers to minimize the cost per good die produced, by accurately screening out-of-spec product early in the process flow. The significant increase in the number of chips on today's 300mm wafers heightens the importance of obtaining reliable in-line data. In addition, the reduction of design rules to 130nm and below is driving precision requirements on metrology to <1nm, in order to maintain acceptable precision-to-tolerance (P/T) ratios. Historical methods of in-line metrology (Low Voltage Scanning Electron Microscopy, Atomic Force Microscopy, Electrical Critical Dimension Measurement) all face limitations with regards to precision, correlation, or throughput. This paper will demonstrate the use of Spectroscopic Ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique is currently being utilized for in-line process control and product disposition, at the gate lithography and etch process steps, on 130nm generation logic devices manufactured in Texas Instruments' DMOS 6 300mm wafer fabrication facility. A brief description of the measurement theory and gate profile measurement solution for both dense and isolated structures will be given. This will be followed by data generated from DMOS 6 production material. Using Spectroscopic Ellipsometry, precision results of <0.5nm for CD and height, and <0.25 degrees for profile sidewall angle were obtained at both the lithography and etch measurement steps. The use of CD and sidewall angle information in an APC loop to improve control over the gate trim etch process will also be discussed. Data will be presented showing univariate and multivariate correlation of gate etch profile parameters to post-metalization transistor drive current (IDrive) that is equivalent or superior to existing metrology techniques. Finally, examples of where Spectroscopic Ellipsometry has both increased sensitivity and shortened response time to gate etch process excursions will be presented.

Proceedings Article | 16 July 2002 Paper

Spectral scatterometry for 2D trench metrology of low-K dual-damascene interconnect

Vladimir Ukraintsev, Mak Kulkarni, Christopher Baum, Karen Kirmse, Marco Guevremont, Suresh Lakkapragada, Kamal Bhatia, Pedro Herrera, Umar Whitney

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473457

KEYWORDS: Scatterometry, Critical dimension metrology, Atomic force microscopy, Scanning electron microscopy, Transmission electron microscopy, Silicon, Metrology, Dielectrics, Reactive ion etching, Semiconducting wafers

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Proceedings Article | 22 August 2001 Paper

Implementation of spectroscopic critical dimension (SCD) (TM) for gate CD control and stepper characterization

John Allgair, David Benoit, Mark Drew, Robert Hershey, Lloyd Litt, Pedro Herrera, Umar Whitney, Marco Guevremont, Ady Levy, Suresh Lakkapragada

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436771

KEYWORDS: Single crystal X-ray diffraction, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Process control, Spectroscopy, Spectroscopes, Metrology, Precision measurement, Control systems

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