The ongoing scaling of semiconductor devices necessitates increasing development of new and disruptive technologies. Curvilinear layout design and optical proximity correction (OPC) are among the innovations facilitating these advancements in technologies. However, they face challenges in mask enablement technology, including issues with mask writing, data volume management, design complexity, mask data representation, mask qualification, and metrology. In this paper, curvilinear mask test patterns and measurement methodologies are newly proposed for mask qualification and masks specification. Using contour-based mask metrology, edge placement error (EPE), mean-to-target (MTT) and uniformity (CDU) based on target maximum curvature (TMC) are measured and used as the main qualification metrics instead of traditional metrics such as critical dimensions (CD). These novel methods will partly complement standard qualification methods used for non-curvilinear (Manhattan) masks. A set of unique mask test structures are also proposed to extract the minimum set of curvilinear mask rules which enables experimental definition and verification of the manufacturing process.
The line edge roughness (LER) of the mask absorber increases as the critical dimension (CD) approaches the mask’s imaging limit. Mask LER has an impact on the corresponding wafer LER, especially in the case of EUV lithography because of the inverse dependence on exposure wavelength. Low-frequency mask LER is transferred directly to the wafer LER while high-frequency mask LER impacts the wafer image by reducing the image log slope (ILS). In this study, we designed a programmed random LER module and fabricated it on a state-of-the-art EUV mask to introduce controlled variations in LER amplitude while maintaining a similar spatial frequency to the reference mask LER. The unbiased 3-σ mask LER was extracted from the 36nm pitch line/space design, showing that programmed LER is transferred to mask LER. The mask was exposed with the ASML NXE:3400B EUV lithography scanner under focus exposure matrix (FEM) conditions. The transfer of mask LER to wafer LER exhibited a similar trend in programmed jog amplitude and step. Wafer LER increases when the exposure conditions deviate from the best dose or best focus, as the mask error enhancement factor (MEEF) increases and is proportional to the LER transfer function. It was observed that programmed LER is filtered through the illumination system, by comparing the power spectral density (PSD) of mask and wafer LER. The programmed LER led to increased wafer defects, specifically, wafer 3-σ unbiased LER above 2.4nm starts to increase wafer defects.
KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Fin field effect transistors, Optical lithography, Front end of line, Manufacturing, Back end of line, Yield improvement, Extreme ultraviolet lithography
A yield prediction model with a corresponding cost of the ownership (CoO) and turn-around-time (TAT) analysis is studied on imec’s advanced technology nodes that include EUV and high NA EUV lithography. It also captures device variations from FinFET to CFET. Using modeled die-yield and the cost-of-ownership (CoO) for imec advanced technology nodes including N2, A14, A10, A7 to A5 technology nodes, we show there is a clear correlation trend in choosing a process technology. A precise methodology that can co-model the turn-around-time (TAT) which is inseparable in evaluating the manufacturability is also provided. As a conclusion, node-to-node scalability is proven to be a function of the manufacturability which will be represented to the yield, CoO and TAT metric, not just a function of the patterning complexity or photolithographic resolution that the industry is mainly chasing after.
KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Manufacturing, Optical lithography, Yield improvement, Front end of line, Semiconductor manufacturing, Performance modeling, Back end of line
In semiconductor manufacturing, yield and cost are important factors to predict and improve the productivity of manufactures. A yield prediction model and the corresponding cost of the ownership with advanced technology nodes beyond imec 5nm are proposed in this paper. In this study, the compact die yield data and the cost will be compared between imec 8nm, 7nm and 5nm technology nodes. With technology nodes scaling, the node-to-node scalability can be impacted by the process complexity, different number of layers, and chip size, etc. With proper process parameters, the yield per layer and the yield per chip can be extracted. In addition, the productivity and turn-around-time (TAT), also called cycle time (CT), can also be calculated based on yield and cost model with complex manufacturing process steps to improve the manufacturability and turnaround-time (TAT). The productivity can be easily evaluated by the yield prediction model since productivity and yield are inseparable in manufacturing. Based on the process assumption, the turn-around-time (TAT) can be precisely estimated by the result of the wafer process time including the time of each step provided by the imec database. As the scaling persists, growing complexity in semiconductor manufacturing gives rise to a concern on the yield and cost. We studied a yield model and the corresponding cost of the ownership for imec technology nodes to discuss their manufacturability. With technology nodes progression, the node-to-node scalability is shown to be impacted by the process complexity from the number of layers, patterning methods and chip size, etc. In addition, productivity and turn-aroundtime (TAT), also referred as the cycle time (CT), can also be estimated to be used as an important parameter to enhance productivity and optimize profitability in semiconductor manufacturing.
KEYWORDS: Extreme ultraviolet, Optical lithography, Metals, Lithography, Extreme ultraviolet lithography, Back end of line, Semiconducting wafers, Standards development, Front end of line, Very large scale integration
The continued need to satisfy the Power-Performance-Area requirements in advanced technologies resulted in a steady and rapid increase in manufacturing costs in the last years. Indeed, novel process integration schemes can require advanced tools and/or new materials, further aggravating cost. In addition, several dimensions are slowing down reaching a plateau due to physical limitations, which can impact the resulting die cost. Therefore, in this work we analyze advanced technology nodes from a cost perspective, considering different patterning and integration schemes at 3 nm and 2 nm node as this is becoming more and more important. Also, possible scenarios regarding the introduction of high-NA EUV lithography at the 2 nm node are explored, showing promising results from both a cost and a yield perspective.
KEYWORDS: Back end of line, Semiconducting wafers, Logic, System integration, 3D imaging standards, 3D modeling, Metals, Front end of line, Computing systems, Information operations
Current Wafer-to-Wafer hybrid bonding process technology allows die stacking with 3D structure pitches in range of 1μm. Independent wafer processing prior to 3D stacking enables heterogeneous CMOS process integration, where each wafer FEOL, BEOL can be optimized for a given functionality to trade-off system performance and cost. Typical functional system partitioning aims the split of the system memory from the logic. While 3D structures with coarser pitches (e.g. micro-bumps) are already used to split the last-level cache (LLC) from the rest of the system (e.g. HBMs), finer 3D structures can be used to split lower and intermediate cache memory layers (L2, L1) from the core logic. System performance gets better since delay and cache latency can be reduced. Also the system cost can be reduced, since only the core layer is now built using the most expensive CMOS process. In this article we quantify the system-level post place and route performance and area benefits of Memory-on-Logic applications using advanced CMOS processes (< 10nm) for various BEOL configuration options, i.e. the number and geometrical properties of different metal layers used in the BEOL stack.
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