The main hurdle in developing new IC technology nodes is the absence of high-quality, comprehensive layouts that can thoroughly test process capabilities, design and process interaction. In the initial stage of process development, it's necessary to define process specifications, specify OPC recipes, and establish design rules to confirm layout manufacturability. Each of these crucial tasks requires chip layouts to assess the quality, precision, and completeness of development outcomes. This paper primarily discusses how to utilize layout slicing to assemble a large layout. It involves cutting the hotspot-free design and contour layouts into slices of different sizes, enriching these slices through flipping, and then randomly assembling the enriched slices to form a large layout.
In the implementation of EUV lithography, the stochastic effects in photoresist patterning are significant. The stochastic characteristic of Chemically Amplified Resist (CAR) for EUV demands novel modeling methods instead of the continuous model used in DUV. The previous model is directly derived from Gillespie algorithm, which sorts all cells into logarithmic classes based on the magnitude of the propensity functions. It takes a lot of time to update the classes in each iteration. Moreover, it splits the whole system only once, and for large systems a logarithmic class can include still larger number of cells, which can also take up a large amount of computing time. In this study, a new stochastic EUV resist model is proposed to improve the speed of PEB simulation by using a modified minimal process algorithm, which employs a splitting method called cascade classification. It divides evenly all cells into small groups in some arbitrary manner and each group is further divided evenly into smaller ones, and so on, until the smallest groups include a sufficiently small number of cells. The research shows that the new algorithm is more efficient than the previous one while maintaining accuracy.
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