In this work, the TiO2 film was deposited on periodic Mo/Si bilayer at various temperatures (70~90°C) by atomic layer deposition (ALD). The H2O and Tetrakis(dimethylamino)titanium (TDMAT) were be used for precursors. Effects of substrate temperature and thickness of TiO2 film on the microstructure, surface roughness, and optical properties were investigated by field emission scanning electron microscopy (FESEM), atomic force microscopy (AFM), high resolution transmission electron microscope (HRTEM), and extreme ultraviolet (EUV) spectrometer, respectively. It was found that the surface roughness of the TiO2 film at substrate temperature 70°C was obviously larger than the others. The surface roughness of TiO2 film was under 0.2nm at the substrate temperature was above 80°C. The reflectivity of periodic Mo/Si bilayer was 66% by EUV spectrometer. We found that the reflectivity of Mo/Si/TiO2 films was decreased with increased the thickness of TiO2 film. The reflectivity of the films was maintain 65.97% as the TiO2 film was 1.8nm. However, the reflectivity of the films was decreased to 59.27% when the TiO2 film was 3nm. Based on the results of the reflectivity investigation, the TiO2 thin film by ALD as the protective film for highly reflective EUV mirror was been confirmed.
In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.
In modern digital integrated-circuit designs, standard-cell libraries are key foundations. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. In this work, as a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristics deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade standard-cell optimization.
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