Metalenses are flat lenses made from thin films with sub-wavelength nano-optical structures that can be created using the same processes that have been developed for integrated circuit manufacturing. We present a workflow that simulates the manufacturing process and enables process engineers and optical designers to study the impact of manufacturing on metalens performance without waiting for multiple manufacture-and-test cycles. To demonstrate this workflow, we design several metalenses and characterize the impact of process variation on absolute focusing efficiency, transmission, and output electric field.
The need for resolution scaling in new device technology nodes is a long-standing trend in semiconductor patterning. As DUV lithography will not go beyond the current 1.35NA and high-NA EUV lithography has not yet been introduced intro production, fabs are pushing to achieve higher resolution in upcoming device nodes by lowering the lithographic k1. DUV lithography is being pushed well below the 80nm minimum pitch value and EUV lithography is also being pushed to continue shrinking beyond current pitch limits. Lower k1 lithography causes increased sensitivity to process variations but tighter EPE control is required in new nodes. Consequently, new methods for improving EPE control and reducing lithographic errors and hotspots are needed well beyond current 2D compact resist modeling applications. This paper discusses new improvements in EPE control and hotspot reduction by improving the accuracy of full-chip three-dimensional (3D)-aware resist compact modeling. These improvements are enabled by better integration and learning for compact models with rigorous 3D resist models that take advantage of enhancements in traditional and machine-learning modeling as well as data handling.
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