Roman Bruck, Yannick De Koninck, Kam-Yan Hon, Peng Sun, Marc Savanier, Subal Sahni, Gianlorenzo Masini, Scott Denton, Laurent Planchon, Thierry Pinguet, Nathaniel Rudnick, Gene Armijo, Joseph Balardeta, Brian Chase, Yuemeng Chi, Anders Dahl, Mehmet Eker, Sama Fathpour, Dennis Foltz, Steve Hovey, Steven Jackson, Wei Li, Yee Liang, Michael Mack, Gary McGee, Simon Pang, Mark Peterson, Kevin Roberson, Jeff Schramm, Chang Sohn, Kirk Stechschulte, George Vastola, Shawn Wang, Gary Wong, Kosei Yokoyama, Shuhuan Yu, Richard Zhou, Attila Mekis, Peter De Dobbelaere
Luxtera and TSMC have jointly developed a new generation 100Gbps/λ-capable silicon photonics platform in a commercial 300 mm CMOS line. We present process details and the performance of the photonic device library.
P. De Dobbelaere, G. Armijo, J. Balardeta, B. Chase, Y. Chi, A. Dahl, Y. De Koninck, S. Denton, M. Eker, S. Fathpour, D. Foltz, F. Gholami, S. Gloeckner, K. Hon, S. Hovey, S. Jackson, W. Li, Y. Liang, M. Mack, G. Masini, G. McGee, A. Mekis, S. Pang, M. Peterson, T. Pinguet, L. Planchon, K. Roberson, S. Sahni, J. Schramm, M. Sharp, C. Sohn, K. Stechschulte, P. Sun, G. Vastola, S. Wang, B. Weber, G. Wong, K. Yokoyama, S. Yu, R. Zhou
In this paper we discuss design and characterization of silicon-photonics-based 100 Gbps (4×26 Gbps) transceivers for parallel single mode fiber communication. We also address some key underlying technologies including silicon photonics wafer processing, photonic device libraries, light source integration and packaging technologies.
Shared shuttle runs are an important factor of the microelectronics business ecosystem, allowing fabless semiconductor
companies to access advanced processes and supporting the development of new tools and processes. We report on the
creation and progress of a shared shuttle program for access to advanced silicon photonics optoelectronic platforms that
we expect will create a similar environment for the field of integrated photonics.
We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics
process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a
hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter
and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used
to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a
design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher
speeds and channel counts.
Ring waveguide resonating structures with high quality factors are the key components servicing silicon
photonic links. We demonstrate highly efficient spectral tunability of the microphotonic ring structures
manufactured in commercial 130 nm SOI CMOS technology. Our rings are fitted with dedicated heaters
and integrated with silicon micro-machined features. Optimized layout and structure of the devices result in
their maximized thermal impedance and increased efficiency of the thermal tuning.
Silicon photonics is envisioned as a promising solution to address the interconnect bottleneck
in large-scale multi-processor computing systems, owing to advantageous attributes such as wide
bandwidth, high density, and low latency. To leverage these advantages, optical proximity coupler is
one of the critical enablers. Chip-to-chip, layer-to-layer optical proximity couplers with low loss,
large bandwidth, small footprint and integration compatibility are highly desirable. In this paper, we
demonstrate chip-to-chip optical proximity coupling using grating couplers. We report the
experimental results using grating couplers fabricated in a photonically-enabled commercial 130nm
SOI CMOS process.
Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy
efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution.
For silicon photonics to prevail and penetrate deeper into the computing system interconnection hierarchy, it requires
innovative optical devices, novel circuits, and advanced integration. We review our recent progress in key building
blocks toward sub pJ/bit optical link for inter/intra-chip applications, ultra-low power silicon photonic transceivers. In
particular, compact reverse biased silicon ring modulator was developed with high modulation bandwidth sufficient for
15Gbps modulation, very small junction capacitance of ~50fF, low voltage swing of 2V, high extinction ratio (>7dB)
and low optical loss (~2dB at on-state). Integrated with low power CMOS driver circuits using low parasitic microsolder
bump technique, we achieved record low power consumption of 320fJ/bit at 5Gbps data rate. Stable operation with biterror-
rate better than 10-13 was accomplished with simple thermal management. We further review the first hybrid
integrated silicon photonic receiver based on Ge waveguide photo detector using the same integration technique, with
which high energy efficiency of 690fJ/bit, and sensitivity of ~18.9dBm at 5Gbps data rate for bit-error-rate of 10-12 were
achieved.
Ring waveguide resonating structures with high quality factors are the key components in the silicon photonics portfolio
boosting up its functionality and circuit performance. Due to a number of manufacturing reasons their peak wavelengths
are often prone to deviate from designed values. In order to keep the ring resonator operating as specified, its peak
wavelength then needs to be corrected in a reliable and power efficient way. We demonstrate the performance of the
thermally tunable mux/demux filter ring structures fabricated in the commercial 130 nm SOI CMOS line.
We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
Finite difference time domain is a powerful numerical method. We review our modeling and design of optical gratings and 2D photonic crystals, aided by the recently developed quartic perfectly matched layer boundary condition. For optical gratings with a quarter wave phase shift, we show that light can be confined in an air bridge micro-cavity. Such devices exhibit sharp transmission resonances in the stop bands. Photonic crystals also demonstrate strong localization of light so waveguides of air can be formed. In addition, even when the bending radius is zero, the transmission exceeds 0.95 percent.
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