Roman Bruck, Yannick De Koninck, Kam-Yan Hon, Peng Sun, Marc Savanier, Subal Sahni, Gianlorenzo Masini, Scott Denton, Laurent Planchon, Thierry Pinguet, Nathaniel Rudnick, Gene Armijo, Joseph Balardeta, Brian Chase, Yuemeng Chi, Anders Dahl, Mehmet Eker, Sama Fathpour, Dennis Foltz, Steve Hovey, Steven Jackson, Wei Li, Yee Liang, Michael Mack, Gary McGee, Simon Pang, Mark Peterson, Kevin Roberson, Jeff Schramm, Chang Sohn, Kirk Stechschulte, George Vastola, Shawn Wang, Gary Wong, Kosei Yokoyama, Shuhuan Yu, Richard Zhou, Attila Mekis, Peter De Dobbelaere
Luxtera and TSMC have jointly developed a new generation 100Gbps/λ-capable silicon photonics platform in a commercial 300 mm CMOS line. We present process details and the performance of the photonic device library.
P. De Dobbelaere, G. Armijo, J. Balardeta, B. Chase, Y. Chi, A. Dahl, Y. De Koninck, S. Denton, M. Eker, S. Fathpour, D. Foltz, F. Gholami, S. Gloeckner, K. Hon, S. Hovey, S. Jackson, W. Li, Y. Liang, M. Mack, G. Masini, G. McGee, A. Mekis, S. Pang, M. Peterson, T. Pinguet, L. Planchon, K. Roberson, S. Sahni, J. Schramm, M. Sharp, C. Sohn, K. Stechschulte, P. Sun, G. Vastola, S. Wang, B. Weber, G. Wong, K. Yokoyama, S. Yu, R. Zhou
In this paper we discuss design and characterization of silicon-photonics-based 100 Gbps (4×26 Gbps) transceivers for parallel single mode fiber communication. We also address some key underlying technologies including silicon photonics wafer processing, photonic device libraries, light source integration and packaging technologies.
We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics
process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a
hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter
and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used
to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a
design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher
speeds and channel counts.
We discuss our approach to monolithic integration of Germanium photodectors with CMOS electronics for high speed
optical transceivers. Integration into the CMOS process and optimization of optical coupling into the devices is described,
followed by a discussion on how the devices are deployed in 4×10 Gbs receiver and transmitter subsystems. We
demonstrate -19 dBm optical sensitivity for a bit error rate of 1e-12. An improvement of several dB resulted from
optimizing the transimpedance amplifier relative to a design that was targeted for hybrid integration with flip-chip
photodetectors, in order to take advantage of the drastically reduced capacitance of the integrated photodetectors (below 20
fF). As an example of how the versatility of on-chip waveguides and integrated photodiodes can be used, we further
describe how the Germanium photodetectors are deployed to obtain a fully autonomous Mach-Zehnder interferometer
subsystem with built-in monitoring and control, that can be instantiated as a single cell in an IC design. A fully differential
layout is implemented for optical, electro-optic and electrical components yielding very small mismatch between
components and enabling control of the interferometer with a minimum penalty.
We describe our approach to the monolithic integration of Ge photodetectors in a photonics-enabled CMOS technology.
Ge waveguide photodetectors allow fast and efficient conversion of optical signals in the near infrared (1.55μm) to the
electrical domain thus enabling the fabrication of compact, high speed (10Gbps) receivers.
We report on the development of single-chip, monolithically-integrated 40 Gbps transceivers built in a 130 nm SOI
CMOS process as part of Phase II of the DARPA EPIC program. In this talk we give an overview of the system
architecture, including the transmit and receive paths as well as the control systems. We report on the performance of
the individual building blocks, and discuss a scaling to 100 Gbps and beyond single-chip transceivers built in CMOS
photonics.
We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
Integration of near infrared (NIR) photodetectors on a silicon substrate is a key step for the fabrication of an all silicon based NIR transceiver. To this extent, polycrystalline germanium (poly-Ge) technology is attractive due to the low deposition temperature and cost. Poly-Ge detectors demonstrated broad response, covering the whole NIR spectrum to 1.55 micron, fast, subnanosecond, speed and excellent versatility. In this work we present our recent results on the integration of a poly-Ge photodetector on a SOI silicon waveguide. The use of a waveguide for light in-coupling is appealing for telecom applications where signal is transported on an optical fibre, but, at the same time, it allows to increase detector responsivity. In fact, in this device the light is absorbed into the thin sensitive layer of the poly-Ge/Si heterojunction in a distributed way, during propagation. This releases the strong constraint of the absorption length being smaller than photocarrier collection length typical of normal incidence photodetectors. In the paper, both design issues and experimental results are reported.
We present a technology for the integration of high performance near-infrared Ge P-I-N photodetectors on Si for Si microphotonics. High quality Ge epilayers were grown on Si by a two-step ultrahigh-vacuum / chemical-vapor-deposition (UHV/CVD) process. Two-step UHV/CVD allows the epitaxial growth of Ge on Si without islanding. Threading-dislocations in Ge epilayers were reduced by cyclic thermal annealing. The reduction of threading-dislocations can be understood in terms of thermal stress induced dislocation glide and reactions. We found that sessile threading-dislocations are not permanent and can be removed.
We report on the integration of Ge p-i-n heterojunction photodiodes on Si substrates. The crucial role of interface defects at the Ge/Si interface on the performance of photodetectors is analyzed and taken into account in the design of the devices. We have designed and fabricated high performance p-i-n Ge photodiodes for the near infrared. Pure Ge is grown by ultra-high-vacuum CVD followed by a cyclic thermal annealing and ion implantation. Devices are fabricated using standard photolithography. The photodiodes exhibit maximum responsivity of 0.8 A/W at 1.3 micrometers and 0.7 A/W at 1.55 micrometers , reverse dark currents in the 20 mA/cm2 range at 1V and response times as short as 520 ps. Our devices are the first p-i-n Ge on Si photodetectors fabricated by CVD and exhibit high performances for a wide range of applications.
Nowadays refractive-index engineering has become a challenging area for experimentalists in semiconductor integrated optics, whereas design constraints are often more strict than both standard technology tolerances and model accuracies. In fact, it is crucial to non-destructively evaluate thicknesses and refractive indices of a multilayer waveguide independently, and to this aim we resorted to X-ray reflectometry and effective index measurements on MBE-grown AlGaAs waveguides, respectively. With the first technique interference effects (Kiessig fringes) arise, which are related to layer thicknesses. By standard data processing, thickness accuracies of +/- 0.05 nm are readily achieved. Effective index measurements were performed at several wavelengths on both slab and rib waveguides, through grating-assisted distributed coupling with both photoresist and etched gratings. Effective indices were determined with an absolute precision as good as 1/2000, adequate for phase matching in parametric devices. Merging thickness and effective index evaluations, the refractive indices of the constituent layers were determined with unprecedented accuracies, in substantial agreement with existing models.
We report on a novel solid state wavelength meter in the near infrared. The device is an array of six photodetectors based on polycrystalline germanium film evaporated on a silicon substrate and each element is a wavelength sensitive detector. We describe the design, the fabrication and the characterization of such device and we demonstrate its capability in the measurement of the wavelength of quasi- monochromatic light beams.
We report the fabrication of fast heterojunction Ge/Si photodetectors which, to the best of our knowledge, exhibit the highest near infrared responsivity at normal incidence reported to date. Such performances are related to the quality of the epitaxial Ge film grown by a two-step UHV-CVD process followed by cyclic thermal annealing. We have measured a fast (FWHM equals 850 ps at 1.3 micrometers ) and efficient (R equals 0.55 A/W at 1.3 micrometers and 0.25 A/W at 1.55 micrometers ) photoresponse. Our technology makes these devices suitable for integration with other electronic and optoelectronic components on Si chips. In the paper we discuss processing technology, material quality, device fabrication and performance measurements.
We report on the fabrication of a detector array for the near infrared on silicon substrate. Thermally evaporated polycrystalline germanium is used as the active layer in the device which consists of 16 pixel with dot-pitch of about 100 micron; the single pixel has a metal-semiconductor-metal structure. We demonstrate a responsivity of 16 mA/W at 1.3 micron and extending down to 1.55 micron. At the same wavelength an operation speed in the nanoseconds range is demonstrated. The overall fabrication process, including substrate cleaning and preparation, requires temperatures lower than 350 degrees Celsius being fully compatible with silicon electronics.
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