Proceedings Article | 10 April 2024
KEYWORDS: Design, Visualization, Instrument modeling, Integrated circuits, Metals, Calibration, Tunable filters, Mathematical optimization, Human-machine interfaces, Digital filtering
This article focuses on the application of Synopsys IC Validator (ICV) Pattern Matching in device extraction for customized devices in Integrated Circuit (IC) design. Customized devices play a critical role in achieving precision models. Having no additional or missing shapes in the region of customized devices is expected in order to keep the precision of models. To address this challenge, a robust methodology with an assistive debugging approach is required. Synopsys IC Validator Pattern Matching offers a solution that not only meets these requirements but also simplifies customized device representation and includes a user-friendly visualized debugger for efficient shape mismatch identification. The article provides a concise explanation of the device extraction flow with pattern matching (Figure 1), emphasizing the use of a pattern library containing source patterns. Pattern matching generates optional marker layers at matched locations by utilizing the pattern library in conjunction with the input design. In the context of Layout vs. Schematic (LVS) flow, the pattern library's source patterns consist of device layers like poly, active, and related layers, which form body and terminal layers. Pattern matching facilitates the extraction of body and terminal layers at matched devices, while any mismatch leads to missing device layers and their absence from the netlist. The effectiveness of IC Validator in delivering expected LVS results is demonstrated through the verification of live designs provided by customers, successfully identifying LVS fails for various design scenarios, including extra/missing/relocated polygons in the device region, extra connections to the outside of the device region, extra connections crossing the device region, pin swapping, and more. Additionally, the article presents a new pattern matching algorithm developed to optimize design turn-around times (TATs) for customized devices, such as inductors and capacitors. The algorithm leverages a multiplesteps pattern matching method, with a particular focus on efficiently filtering candidate target patterns. Through adjustments to the clipping-size in the first pattern matching step, a significant ~1.5x performance enhancement is achieved. In conclusion, the integration of pattern matching in device extraction proves to be a valuable approach, ensuring accurate IC design and validation by effectively handling customized devices. The enhanced pattern matching algorithm further optimizes design TATs, contributing to improved overall efficiency in IC design workflows.
