Dr. Soo-Han Choi Profile

Dr. Soo-Han Choi

Principal at Synopsys Inc.

SPIE Involvement:

Author

Publications (37)

Proceedings Article | 12 November 2024 Presentation + Paper

Design and process-friendly High-NA EUV stitching options

Kevin Lucas, Zachary Levinson, Yunqiang Zhang, Xiangyu Zhou, Kevin Hooker, Linghui Wu, Lin Wang, Michael Lam, Soo-Han Choi, James Ban

Proceedings Volume 13216, 132161U (2024) https://doi.org/10.1117/12.3034869

KEYWORDS: Design, Optical lithography, Design rules, Scanners, Printing, Extreme ultraviolet lithography, Extreme ultraviolet, SRAF, Semiconducting wafers

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Proceedings Article | 10 April 2024 Presentation + Paper

Advanced device extraction and LVS (layout vs. schematic) with pattern matching applications

Hsiang-Chih Wen, Soo Han Choi, Antonio Ferrario, David DeMarcos, Pixy Pi, Selwyn Gao, Shirley Xue, Elango Velayutham, Mark Pogers, Anil Karanam

Proceedings Volume 12954, 129540A (2024) https://doi.org/10.1117/12.3009824

KEYWORDS: Design, Visualization, Instrument modeling, Integrated circuits, Metals, Calibration, Tunable filters, Mathematical optimization, Human-machine interfaces, Digital filtering

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This article focuses on the application of Synopsys IC Validator (ICV) Pattern Matching in device extraction for customized devices in Integrated Circuit (IC) design. Customized devices play a critical role in achieving precision models. Having no additional or missing shapes in the region of customized devices is expected in order to keep the precision of models. To address this challenge, a robust methodology with an assistive debugging approach is required. Synopsys IC Validator Pattern Matching offers a solution that not only meets these requirements but also simplifies customized device representation and includes a user-friendly visualized debugger for efficient shape mismatch identification. The article provides a concise explanation of the device extraction flow with pattern matching (Figure 1), emphasizing the use of a pattern library containing source patterns. Pattern matching generates optional marker layers at matched locations by utilizing the pattern library in conjunction with the input design. In the context of Layout vs. Schematic (LVS) flow, the pattern library's source patterns consist of device layers like poly, active, and related layers, which form body and terminal layers. Pattern matching facilitates the extraction of body and terminal layers at matched devices, while any mismatch leads to missing device layers and their absence from the netlist. The effectiveness of IC Validator in delivering expected LVS results is demonstrated through the verification of live designs provided by customers, successfully identifying LVS fails for various design scenarios, including extra/missing/relocated polygons in the device region, extra connections to the outside of the device region, extra connections crossing the device region, pin swapping, and more. Additionally, the article presents a new pattern matching algorithm developed to optimize design turn-around times (TATs) for customized devices, such as inductors and capacitors. The algorithm leverages a multiplesteps pattern matching method, with a particular focus on efficiently filtering candidate target patterns. Through adjustments to the clipping-size in the first pattern matching step, a significant ~1.5x performance enhancement is achieved. In conclusion, the integration of pattern matching in device extraction proves to be a valuable approach, ensuring accurate IC design and validation by effectively handling customized devices. The enhanced pattern matching algorithm further optimizes design TATs, contributing to improved overall efficiency in IC design workflows.

Proceedings Article | 23 March 2020 Presentation + Paper

Multi-varied implementations with common underpinnings in design technology co-optimization

Kevin Lucas, Victor Moroz, John Kim, Soo-Han Choi, Tim Tsuei

Proceedings Volume 11328, 113280Y (2020) https://doi.org/10.1117/12.2553656

KEYWORDS: Device simulation, Optical lithography, Silicon, Semiconducting wafers, Process modeling, Visualization, Lithography, Design for manufacturing

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Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.

Proceedings Article | 20 March 2019 Presentation + Paper

SAQP spacer merge and EUV self-aligned block decomposition at 28nm metal pitch on imec 7nm node

Jae Uk Lee, Soo Han Choi, Yasser Sherazi, Ryan Ryoung Han Kim

Proceedings Volume 10962, 109620N (2019) https://doi.org/10.1117/12.2515216

KEYWORDS: Metals, Optical lithography, Extreme ultraviolet, Extreme ultraviolet lithography, Etching, Source mask optimization, Stochastic processes, Photomasks, Lithography, Error analysis

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Self-aligned quadruple patterning (SAQP) is not compatible with every design. It couldn’t pattern even number routing track, for examples 4 internal routing tracks with power rails side by side, due to the process footprint of conventional SAQP. On the other hand SAQP spacer merge technique is able to remove 1 internal metal line by merging 2 spacer into 1 spacer. It can offer additional track scaling and flexible design of track number, for example, 5.5 tracks together with 6.5 tracks to accomplish low and high performance device respectively. In this paper, SAQP spacer merge technique and self-aligned block (SAB) process are considered as one of potential patterning approaches for 1D style 28 nm metal pitch. SAQP spacer merge technique is indispensable for supporting 5.5T cell of 4 internal tracks with 28nm metal pitch. And 5.5T cell also requires the irregular metal color array for SAB and its biases which is litho-etch skew. SAB can be sized up double compared to conventional block process, it is biased over next metal line to takes advantage of material etch selectivity of SAQP structure inherently before metallization. To meets those requirement with automatic mask layout generation, we newly proposed forward decomposition algorithm and color-aware block resizing of SAB. The forward decomposition algorithm generates mandrel to spacer 1 to spacer 2 to mimics process order of SAQP spacer merge technique. And color-aware block resizing of SAB needs conditional bias depending on neighboring metal color. Additionally, edge placement error budget is analyzed with process variation band of source mask optimization (SMO) on top of overlay, line edge roughness (LER) and etch uniformity assumption. Simulation result seems to be fine to enable SAQP spacer merge and SAB integration. However, EUV stochastics reported that CD uniformity is not fit in Gaussian distribution. Considering beyond 3σ, restricted design rule may be needed. To see design availability, 3 representative standard library cells were verified in design rule restriction without area loss. This SAQP spacer merge decomposition algorithm is useful since it is possible to extend for Fin patterning application as well.

Proceedings Article | 28 March 2017 Paper

Stitching-aware in-design DPT auto fixing for sub-20nm logic devices

Soo-Han Choi, Sai Krishna K.V.V.S, David Pemberton-Smith

Proceedings Volume 10148, 1014818 (2017) https://doi.org/10.1117/12.2262836

KEYWORDS: Electron beam lithography, Manufacturing, Lithography, Extreme ultraviolet lithography, 193nm lithography, Immersion lithography, Metals, Logic devices, Double patterning technology, Algorithm development

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As the technology continues to shrink below 20nm, Double Patterning Technology (DPT) becomes one of the mandatory solutions for routing metal layers. From the view point of Place and Route (P&R), the major concerns are how to prevent DPT odd-cycles automatically without sacrificing chip area. Even though the leading-edge P&R tools have advanced algorithms to prevent DPT odd-cycles, it is very hard to prevent the localized DPT odd-cycles, especially in Engineering Change Order (ECO) routing. In the last several years, we developed In-design DPT Auto Fixing method in order to reduce localized DPT odd-cycles significantly during ECO and could achieve remarkable design Turn-Around Times (TATs). But subsequently, as the design complexity continued increasing and chip size continued decreasing, we needed a new In-design DPT Auto Fixing approach to improve the auto. fixing rate.

In this paper, we present the Stitching-Aware In-design DPT Auto Fixing method for better fixing rates and smaller chip design. The previous In-design DPT Auto Fixing method detected all DPT odd-cycles and tried to remove oddcycles by increasing the adjacent space. As the metal congestions increase in the newer technology nodes, the older Auto Fixing method has limitations to increase the adjacent space between routing metals. Consequently, the auto fixing rate of older method gets worse with the introduction of the smaller design rules. With DPT stitching enablement at In-design DRC checking procedure, the new Stitching-Aware DPT Auto Fixing method detects the most critical odd-cycles and revolve the odd-cycles automatically. The accuracy of new flow ensures better usage of space in the congested areas, and helps design more smaller chips.

By applying the Stitching-Aware DPT Auto Fixing method to sub-20nm logic devices, we can confirm that the auto fixing rate is improved by ~2X compared with auto fixing without stitching. Additionally, by developing the better heuristic algorithm and flow for DPT stitching, we can get DPT compliant layout with the acceptable design TATs.

Proceedings Article | 18 March 2015 Paper

An efficient auto TPT stitch guidance generation for optimized standard cell design

Nagaraj Samboju, Soo-Han Choi, Srini Arikati, Erdem Cilingir

Proceedings Volume 9427, 94270A (2015) https://doi.org/10.1117/12.2085834

KEYWORDS: Standards development, Electron beam lithography, Lithography, Legal, Manufacturing, 193nm lithography, Optical lithography, Immersion lithography, Extreme ultraviolet lithography, Printing

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As the technology continues to shrink below 14nm, triple patterning lithography (TPT) is a worthwhile lithography methodology for printing dense layers such as Metal1. However, this increases the complexity of standard cell design, as it is very difficult to develop a TPT compliant layout without compromising on the area. Hence, this emphasizes the importance to have an accurate stitch generation methodology to meet the standard cell area requirement as defined by the technology shrink factor. In this paper, we present an efficient auto TPT stitch guidance generation technique for optimized standard cell design. The basic idea here is to first identify the conflicting polygons based on the Fix Guidance [1] solution developed by Synopsys. Fix Guidance is a reduced sub-graph containing minimum set of edges along with the connecting polygons; by eliminating these edges in a design 3-color conflicts can be resolved. Once the conflicting polygons are identified using this method, they are categorized into four types [2] - (Type 1 to 4). The categorization is based on number of interactions a polygon has with the coloring links and the triangle loops of fix guidance. For each type a certain criteria for keep-out region is defined, based on which the final stitch guidance locations are generated. This technique provides various possible stitch locations to the user and helps the user to select the best stitch location considering both design flexibility (max. pin access/small area) and process-preferences. Based on this technique, a standard cell library for place and route (P and R) can be developed with colorless data and a stitch marker defined by designer using our proposed method. After P and R, the full chip (block) would contain the colorless data and standard cell stitch markers only. These stitch markers are considered as “must be stitch” candidates. Hence during full chip decomposition it is not required to generate and select the stitch markers again for the complete data; therefore, the proposed method reduces the decomposition time significantly.

Proceedings Article | 8 November 2012 Paper

Double patterning for 20nm and beyond: design rules aware splitting

Tamer Desouky, David Abercrombie, Hojun Kim, Soo-Han Choi

Proceedings Volume 8522, 852221 (2012) https://doi.org/10.1117/12.946589

KEYWORDS: Double patterning technology, Optical lithography, Visualization, Acquisition tracking and pointing, Photomasks, Legal, Lithography, Lab on a chip, Electronic design automation, Detection and tracking algorithms

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Proceedings Article | 8 November 2012 Paper

Novel DPT methodology co-optimized with design rules for sub-20nm device

Hyun-Jong Lee, Soo-Han Choi, Jae-Seok Yang, Kwan-Young Chun, Jeong-ho Do, Chul-Hong Park

Proceedings Volume 8522, 85220T (2012) https://doi.org/10.1117/12.964976

KEYWORDS: Optical lithography, Critical dimension metrology, Source mask optimization, Photomasks, Double patterning technology, Resolution enhancement technologies, Lithography, Lithographic illumination, Extreme ultraviolet

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Proceedings Article | 5 April 2011 Paper

Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Yu-Jin Pyo, Soo-Han Choi, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo, Gyu-Tae Kim

Proceedings Volume 7974, 797413 (2011) https://doi.org/10.1117/12.869978

KEYWORDS: Critical dimension metrology, Optical lithography, Lithography, Error analysis, Photomasks, Monte Carlo methods, Capacitance, Overlay metrology, Resistance, Transistors

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Proceedings Article | 4 April 2011 Paper

Layout decomposition of self-aligned double patterning for 2D random logic patterning

Yongchan Ban, Alex Miloslavsky, Kevin Lucas, Soo-Han Choi, Chul-Hong Park, David Pan

Proceedings Volume 7974, 79740L (2011) https://doi.org/10.1117/12.879500

KEYWORDS: Photomasks, Metals, Lithography, Optical lithography, Logic, Etching, Double patterning technology, Manufacturing, Semiconducting wafers, Lithographic illumination

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Proceedings Article | 4 April 2011 Paper

New double patterning technology for direct contact considering patterning margin and electrical performance

Soo-Han Choi, A-Young Je, Jae-Seok Yang, Chul-Hong Park, Sang-Hoon Lee, Young-Kwan Park

Proceedings Volume 7974, 79740H (2011) https://doi.org/10.1117/12.879125

KEYWORDS: Transistors, Photomasks, Algorithm development, Optical lithography, Double patterning technology, Critical dimension metrology, Analog electronics, Lithography, Extreme ultraviolet lithography, Etching

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As the optical lithography advances into the sub-30nm technology node, many candidates of the lithography have been discussed. Double pattering technology (DPT) has been a primary lithography candidate for the direct contact of the sub-30nm device due to a merit of a low mask cost and process stability compared to the extreme ultraviolet lithography (EUV). However, the major concerns of DPT are the critical dimension (CD) skew and overlay error between the 1st and 2nd pattering, which cause the degradation of electrical performance such as the mismatch of the pair transistors of the analog circuit. If we assume there is the 10nm position difference of the direct contact between the pair transistors, which is induced by the overlay error between the 1st and 2nd pattering of the DPT process, then the threshold voltage difference between the pair transistors is about 10%. Therefore, the direct contact of the pair transistors must be decomposed as the same color to minimize the threshold voltage variation of the analog circuit. Since the DPT process of the direct contact is the litho-etch-litho-etch (LELE) process, there are the CD variations induced by the global density difference between the 1st and 2nd mask. In this paper, we newly develop the DPT methodology to decompose the direct contact of the pair transistors to the same mask using the optimized marking polygons, decomposition algorithm. In addition, the decomposition algorithm for the density balancing between the 1st and 2nd mask is developed to minimize the CD variations caused by the density difference. Our main contributions are as follows. (1) The optimal marking polygons, which group the direct contacts of the pair transistors, are designed to consider the layout configurations of pair transistors. The space between each contact located on the same marking polygon is designed to be larger than the resolution limit of the single exposure, so that the contacts grouped by the same marking polygon can be decomposed as the same color. (2) The whole contacts grouped by the same marking polygon are changed to the representative single contact, and then the colors of the grouped contacts are assigned by the representative single contact and its surrounded contacts. (3) After decomposing the layout to consider the contact on the pair transistors, the remaining contacts, which is not necessary to decompose from the view point of the patterning limit, are decomposed to satisfy the density balance between the 1st and 2nd mask. Consequently, we can achieve the pattering margin and electrical performance of sub-30nm device by applying the new DPT methodology to the direct contact.

Proceedings Article | 29 September 2010 Paper

Model-based double dipole lithography for sub-30nm node device

A-Young Je, Soo-Han Choi, Jeong-Hoon Lee, Ji-Young Lee, James Word, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo, Gyu-Tae Kim

Proceedings Volume 7823, 78230Z (2010) https://doi.org/10.1117/12.864081

KEYWORDS: Photomasks, Lithography, Model-based design, Image processing, Optical proximity correction, Metals, Manufacturing, Optical lithography, Lithographic illumination, Instrument modeling

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As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL requirements have been also emerged to improve the process margin and to reduce the mask-enhanced error factor (MEEF), which is to maximize the resolution and image contrast. There are two approaches in DDL i.e. model basedand rule based-DDLs. Rule-based DDL, in which the patterns are decomposed by the simple rules such as x- and ydirectional rules, shows the low process margin in the 2-dimension (2D) patterns, i.e., line-end to line-end, line-end to bar and semi-isolated bars. In this paper, we first present various analyses of our new model-based DDL (MBDDL) method. Our goal is to maximize the process margin of the 2D patterns. Our main contributions are as follows. (1) We generate new 2D test patterns including various configurations of the metal layer. The new 2D patterns can be used to optimize the parameters of the MBDDL and to build the good design rules. The purpose of building the good design rules is improving the process margin of the certain 2D patterns with the low process margin in spite of optimizing the parameters of MBDDL. (2) We optimize the initial layout decomposition, which is the first step of MBDDL and affects the whole of MBDDL quality. In addition, the model-based decomposition is applied with the process-window OPC (PWOPC) in terms of the criteria of edge placement error (EPE) and mask rule checking (MRC) violation. Our new model-based approach including the newly designed test patterns and optimized decomposition parameters leads to the improved depth of focus (DOF) and enhanced the exposure latitude (EL). We achieve the 80nm DOF, which is the manufacturable margin for the metal 1 layer at the sub-30nm node.

Proceedings Article | 13 March 2009 Paper

Uniformity-aware standard cell design with accurate shape control

Hongbo Zhang, Martin Wong, Kai-Yuan Chao, Liang Deng, Soo-Han Choi

Proceedings Volume 7275, 72751G (2009) https://doi.org/10.1117/12.814445

KEYWORDS: Printing, Light sources, Double patterning technology, Standards development, Lithography, Metals, Resolution enhancement technologies, Manufacturing, Very large scale integration, Photomasks

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Proceedings Article | 14 May 2007 Paper

DFM based on layout restriction and process window verification for sub-60-nm memory devices

Soo-Han Choi, Dai-Hyun Jung, Ji-Suk Hong, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6607, 66071A (2007) https://doi.org/10.1117/12.728958

KEYWORDS: Data modeling, Lithography, Critical dimension metrology, Process modeling, Design for manufacturing, Finite element methods, Photoresist processing, Photomasks, Optical proximity correction, Data processing

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The adoption of the model-based OPC and RET does not guarantee enough process margin any more in the low k1 lithography because potential patterning defects by layout-induced hot spots reduce common process window. The introduction of the litho-friendly layout has faced practical limitation by the designers' short knowledge of the lithography and its impact on the layout. In this paper, we develop a novel method based on restricted design rules (RDR) and process window verification (PWV) to get rid of the layout-related process hot spots during the physical layout design. Since RDR consists of simple design rules familiar to designers and PWV is implemented on layout editor environment, this proposed method is easy to apply in the current design flow. Since memory core layout is designed with typical and repeated patterns, the restriction of layout by design rule enforcement is effective to remove hot spots in the core area. We develop a systematic RDR extraction method by designing test patterns representing repeated memory core patterns by simple pattern matching technique. 1-dimensional (1D, simple line and space pattern) and 1.5-dimensional (1.5D, complicated line and space pattern) test patterns are analyzed to take into account the printability. The 2-dimension (2D) test patterns split by contact pad size are designed to consider the overlap margin between related layers. After removing the hot spots with RDR violations on unit cell by auto-fixer, PWV is applied to detect the random hot spots located on peripheral area. Analyzing CD difference between measurement and simulation according to variation of resist cutting plane and focus, the optical model having physical meaning is generated. The resist model, which uses focus exposure matrix (FEM) data within the process margin of memory cell, can represent the photo process variations accurately. Implementing the proposed method based on RDR and PWV, depth of focus (DOF) of sub-60nm memory device is improved by 50% compared with the result of original layout.

Proceedings Article | 20 October 2006 Paper

Required mask specification for mass production devices below 65-nm design node

Dongseok Nam, Soohan Choi, Jonggul Doh, Young-hwa Noh, Hojune Lee, Yu-jeung Sin, Bo-hye Kim, Man-kyu Kang, Byunggook Kim, Seong-woon Choi, Woosung Han

Proceedings Volume 6349, 634928 (2006) https://doi.org/10.1117/12.686534

KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Tolerancing, Photoresist processing, Optical proximity correction, Mask making, Semiconductors, Manufacturing, Computer simulations

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Proceedings Article | 15 March 2006 Paper

MEEF-based correction to achieve OPC convergence of low-k1 lithography with strong OAI

Soo-Han Choi, A-Young Je, Ji-Suk Hong, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6154, 61540P (2006) https://doi.org/10.1117/12.656894

KEYWORDS: Optical proximity correction, Critical dimension metrology, Lithography, Lithographic illumination, Model-based design, Photomasks, Device simulation, Solid modeling, Immersion lithography, Nanoimprint lithography

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Proceedings Article | 12 May 2005 Paper

Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600249

KEYWORDS: Nanoimprint lithography, Photomasks, Optical proximity correction, Semiconducting wafers, Lithographic illumination, Lithography, Thin films, Scanners, Model-based design, SRAF

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Proceedings Article | 28 May 2004 Paper

Fulfillment of model-based OPC for contact patterns in 60-nm level logic device

Sang-Wook Kim, Sung-Woo Lee, Chang-Min Park, Soo-Han Choi, Young-Mi Lee, Yool Kang, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536268

KEYWORDS: Optical proximity correction, Logic devices, Model-based design, Critical dimension metrology, Instrument modeling, Data modeling, Transistors, Resistance, Materials processing, Optical lithography

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Proceedings Article | 28 May 2004 Paper

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

Ji-Suk Hong, Chul-Hong Park, Dong-Hyun Kim, Soo-Han Choi, Yong-Chan Ban, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535027

KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Critical dimension metrology, Instrument modeling, Etching, Process modeling, Lithography, Calibration, Error analysis

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Proceedings Article | 28 May 2004 Paper

Simulation-based critical-area extraction and litho-friendly layout design for low k1 lithography

Soo-Han Choi, Yong-Chan Ban, Ki-Heung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535008

KEYWORDS: Optical proximity correction, Lithography, Solid modeling, Photomasks, Image processing, Critical dimension metrology, Nanoimprint lithography, Semiconducting wafers, Electroluminescence, SRAF

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Proceedings Article | 24 May 2004 Paper

Assessments on process parameters' influences to the proximity correction

Eun-Mi Lee, Sung-Woo Lee, Doo-Youl Lee, Soo-Han Choi, Joo-On Park, Sung-Gon Jung, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536341

KEYWORDS: Optical proximity correction, Critical dimension metrology, Atrial fibrillation, Cadmium, Resolution enhancement technologies, Data modeling, Logic devices, Photomasks, Line edge roughness, Scanning electron microscopy

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Proceedings Article | 26 June 2003 Paper

Hybrid PPC methodology using multistep correction and implementation for the sub-100-nm node

Soo-Han Choi, Ji-Soong Park, Chul-Hong Park, Won-Young Chung, In-sung Kim, Dong-Hyun Kim, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485397

KEYWORDS: SRAF, Etching, Critical dimension metrology, Logic devices, Process control, Process modeling, Semiconductors, Control systems, Plasma, Instrument modeling

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Proceedings Article | 30 July 2002 Paper

Hybrid PPC methodology and implementation in the correction of etch proximity

Chul-Hong Park, Sang-Uhk Rhie, Soo-Han Choi, Dong-Hyun Kim, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474586

KEYWORDS: Critical dimension metrology, Etching, Model-based design, Instrument modeling, Performance modeling, Image segmentation, Data modeling, Cadmium, Data corrections, Lithography

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Proceedings Article | 21 May 1996 Paper

Accurate overlay control for 0.30-um i-line lithography

KeunYoung Kim, Ikboum Hur, Gook-Jin Jang, Soo-Han Choi

Proceedings Volume 2725, (1996) https://doi.org/10.1117/12.240098

KEYWORDS: Photomasks, Semiconducting wafers, Reticles, Distortion, Image registration, Lithography, Overlay metrology, Mask making, Quartz, Data modeling

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Proceedings Article | 26 May 1995 Paper

Study of optical proximity effects using off-axis illumination with attenuated phase shift mask

Chang-Nam Ahn, Ki-Ho Baik, Yong-Suk Lee, Hung-Eil Kim, Ikboum Hur, YoungSik Kim, Ju-Hwan Kim, Soo-Han Choi

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209254

KEYWORDS: Transmittance, Photomasks, Phase shifts, Lithography, Super resolution, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Scanning electron microscopy, Optical lithography

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Proceedings Article | 26 May 1995 Paper

Implementation of i-line lithography to 0.30 um design rules

KeunYoung Kim, Hung-Eil Kim, Il-Ho Lee, Jin-Soo Kim, Jun-Sung Chun, Ikboum Hur, Seung-Chan Moon, Ki-Ho Baik, Soo-Han Choi

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209286

KEYWORDS: Lithography, Deep ultraviolet, Photomasks, Chromium, Photoresist processing, Phase shifts, Resist chemistry, Optical lithography, Chemically amplified resists, Critical dimension metrology

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The optical lithography is extending its life by combining high numerical aperture (NA) optics and shorter wavelength. The shorter wavelength lithography has required the new developments of related technologies. In particular, DUV resists require an entirely different resist chemistry. Much progress has been demonstrated in the field of transparent chemically amplified resists with high sensitivity. However, this DUV lithography ((lambda) equals 248 nm) has been delayed for mass production due to their limitations, such as (i) delay time effects, (ii) high cost ownership due to expensive resist materials and laser maintenance, and (iii) critical dimension (CD) variation over topography caused by multireflection of topographic features. On the other hand, i- line lithography ((lambda) equals 365 nm) has apparently been applied to 64M DRAM of 0.35 micrometers design rule, and attempted to 0.30 micrometers technology which corresponds to 2nd generation 64M DRAM or 1st generation 256 M DRAM. It might be achieved by combination of off-axis illumination (OAI), phase shift mask (PMS) and advanced resist process technique of i-line lithography. Therefore, i-line lithography can be more practical method rather than DUV lithography for the mass production. In this paper, we have optimized the i-line lithographic techniques for the various pattern shape and density for 0.30 micrometers design rule. Optimum duty ratio was tried to find for line and space, contact hole patterns. The basic rule is to keep the minimum Cr width over 0.30 micrometers mask. OAI have been applied to get higher contrast of line and space, and even contact hole patterns, and achieve good pattern fidelities of island patterns. By the implementation of OAI, process latitudes were greatly improved compared to that of conventional techniques. In order to optimize the process over the actual topography, optimum numerical aperture (NA) and aperture of the OAI were selected. In conclusion, 0.30 micrometers design rule device was successfully fabricated by optimizing the advanced i-line lithographic techniques.

Proceedings Article | 26 May 1995 Paper

Effect of pattern density for contact windows in an attenuated phase shift mask

Ikboum Hur, Ju-Hwan Kim, Il-Ho Lee, Hung-Eil Kim, Chang-Nam Ahn, Ki-Ho Baik, Soo-Han Choi

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209260

KEYWORDS: Transmittance, Lithography, Photomasks, Phase shifts, Semiconducting wafers, Scanning electron microscopy, Photomicroscopy, Phase shifting, Optical lithography, Mask making

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Proceedings Article | 22 May 1995 Paper

Effective alignment technique and its implementation to enhance total overlay accuracy on highly reflective films

Young-Hong Min, Seung-Chan Moon, Hyeong-Soo Kim, Ki-Ho Baik, Soo-Han Choi

Proceedings Volume 2439, (1995) https://doi.org/10.1117/12.209212

KEYWORDS: Optical alignment, Aluminum, Sputter deposition, Semiconducting wafers, Sensors, Reflectivity, Data transmission, Overlay metrology, Surface roughness, Metals

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Proceedings Article | 9 September 1994 Paper

Surface charging effect on microloading for sub-quarter-micron contact etching

Ki-Soo Shin, Hae-Sung Park, Soo-Han Choi

Proceedings Volume 2335, (1994) https://doi.org/10.1117/12.186074

KEYWORDS: Etching, Photomasks, Ions, Plasma, Oxides, Semiconducting wafers, Argon, Scanning electron microscopy, Polymers, Magnetism

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Proceedings Article | 17 May 1994 Paper

Overlay and lens distortion in a modified illumination stepper

Chul-Seung Lee, Jeong Soo Kim, Ikboum Hur, Young-Mog Ham, Soo-Han Choi, YeonSeon Seo, Scott Ashkenaz

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175404

KEYWORDS: Distortion, Error analysis, Reticles, Lithographic illumination, Photomasks, Semiconducting wafers, Image processing, Phase shifts, Image resolution, Astatine

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Proceedings Article | 17 May 1994 Paper

Quarter-micrometer i-line lithography using an alternating phase-shift mask

Hung-Eil Kim, YoungSik Kim, Chul-Seung Lee, Young-Mog Ham, Dong-Jun Ahn, Soo-Han Choi

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175457

KEYWORDS: Photomasks, Phase shifts, Lithography, Transmittance, Critical dimension metrology, Optical lithography, Lithographic illumination, Phase shifting, Reticles, Photoresist materials

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Proceedings Article | 17 May 1994 Paper

Fundamental analysis on fabrication of 256-MB DRAM using phase-shift mask technology

Young-Mog Ham, YoungSik Kim, Ikboum Hur, Ki-Yeop Park, Hung-Eil Kim, Dong-Jun Ahn, Soo-Han Choi

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175419

KEYWORDS: Photomasks, Photoresist processing, Phase shifts, Transmittance, Image processing, Semiconducting wafers, Lithography, Process control, Metals, Phase shifting

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Proceedings Article | 16 May 1994 Paper

Characterization of the quarter-micron i-line lithography using a top surface imaging process

Seung-Chan Moon, Hyeong-Soo Kim, Chang-Moon Lim, Tai-Kyung Won, Soo-Han Choi

Proceedings Volume 2195, (1994) https://doi.org/10.1117/12.175354

KEYWORDS: Image processing, Lithography, Polymers, Optical lithography, Photoresist materials, Silicon, Lithographic illumination, Critical dimension metrology, Prototyping, Photoresist processing

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Proceedings Article | 1 May 1994 Paper

Quantitive analysis of the proximity effect in optical lithographic process

Sang-Man Bae, Hung-Eil Kim, Young-Mog Ham, Seung-Chan Moon, Soo-Han Choi

Proceedings Volume 2196, (1994) https://doi.org/10.1117/12.174128

KEYWORDS: Lithography, Photoresist processing, Critical dimension metrology, Very large scale integration, Optical lithography, Semiconducting wafers, Photoresist developing, Photoresist materials

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Proceedings Article | 1 May 1994 Paper

Process-induced effects on the intrafield overlay error

Young-Mog Ham, Chul-Seung Lee, YoungSik Kim, Dong-Jun Ahn, Soo-Han Choi, YeonSeon Seo, Mark Merrill

Proceedings Volume 2196, (1994) https://doi.org/10.1117/12.174138

KEYWORDS: Overlay metrology, Deposition processes, Etching, Optical alignment, Molybdenum, Integrated circuits, Error analysis, Lithography, Semiconducting wafers, Oxidation

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Proceedings Article | 15 February 1994 Paper

Magnetically enhanced reactive ion etching of silylated resist in O2/Ar mixtures

Myung-Seon Kim, Jin-Woong Kim, Jun-mo Kim, Yeo-Song Seol, Hae-Sung Park, Soo-Han Choi

Proceedings Volume 2091, (1994) https://doi.org/10.1117/12.167338

KEYWORDS: Etching, Photoresist processing, Plasma, Argon, Oxygen, Reactive ion etching, Photomasks, Ions, Magnetism, Photoresist developing

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Proceedings Article | 15 September 1993 Paper

Influence of process parameters on the lithographic performance characterization in the top imaging process by silylation

Tai-Kyung Won, Seung-Chan Moon, Hyeong-Soo Kim, Jin-Woong Kim, Myung-Seon Kim, Dong-Jun Ahn, Soo-Han Choi

Proceedings Volume 1925, (1993) https://doi.org/10.1117/12.154804

KEYWORDS: Photoresist processing, Image processing, Lithography, Photoresist materials, Diffusion, Silicon, Photoresist developing, Magnetism, Photomasks, Oxygen

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Showing 5 of 37 publications

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