The semiconductor industry has witnessed a fast progression of spectroscopic ellipsometry (SE) techniques aimed at resolving a plethora of complex device characterizations on a nanometric scale. The Mueller Matrix (MM) methodology coupled with rigorous coupled-wave analysis (RCWA) has offered an unprecedented power of investigation and analysis of diverse critical dimensions (CDs), especially when applied to gate-all-around (GAA) structures, as it helps increase the useful spectral signals of the often geometrically buried CDs. However, the sensitivity to the CDs can be often screened by other parameters, hampering the precision and accuracy of the measurement. Combining the most sensitive MM elements has therefore become a critical step of scatterometry critical dimension (SCD) metrology. Driven by the rapid developments of Machine Learning (ML) algorithms, we propose a versatile ellipsometry methodology that overcomes poor sensitivity and increases accuracy through a novel principal component analysis (PCA) method of the ML training algorithm with RCWA assistance. Furthermore, our methodology introduces a new ML training concept based on reference data statistics, rather than raw reference. Our approach has been validated with reference data and proved successful in monitoring GAA sheet-specific indent. The proposed methodology paves the way to measuring low sensitivity CDs with highly accurate, noise-reduced and robust ML-based physical SCD models for any logic and memory application.
A spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective analyses of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows for focusing on parameters of interest through dramatically simplified optical modeling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are monitored discussed: (i) the critical dimensions (CDs) of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) the CDs of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy. Furthermore, it was shown that machine learning models trained with VTS filtered data can converge to a robust solution with a smaller dataset compared with models training with traditional scatterometry data.
KEYWORDS: Metrology, Semiconducting wafers, Scatterometry, Optical filters, Dielectrics, Data modeling, Back end of line, Front end of line, Chemical mechanical planarization, Transmission electron microscopy
In this work, a novel spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective measurements of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows focusing on parameters of interest through dramatically simplified optical modelling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are discussed in this paper: monitoring (i) critical dimensions of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) critical dimensions of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy.
Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured the focus of the semiconductor industry and have been identified as the lead architecture to continue logic complementary metal-oxide-semiconductor scaling beyond 5 nm node. The fabrication of GAA devices requires specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology progresses through research and development cycles and is poised to transition to manufacturing, there are many opportunities and challenges that still remain for in-line metrology. Especially valuable are measurement techniques that are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact on the frequency of cycles of learning. More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. Thanks to the computing revolution the semiconductor industry enabled, machine learning has begun to permeate in-line disposition, and hybrid metrology systems continue to advance. Of course, metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness, pitch walk, and defectivity continue to be managed. We review related prior studies and advocate for future metrology development that ensures nanosheet technology has the in-line data necessary for success.
In this work, the novel enhancement to multichannel scatterometry data collection, Spectral Interferometry, is introduced and discussed. The Spectral Interferometry technology adds unique spectroscopic data by providing absolute phase information. This enhances metrology performance by improving sensitivity to weak target parameters and reducing parameter correlations. Spectral Interferometry enhanced OCD capabilities were demonstrated for one of the most critical and challenging applications of gate-all-around nanosheet device manufacturing: lateral etching of SiGe nanosheet layers to form inner spacer indentations. The inner spacer protects the channel from the source/drain regions during channel release and defines the gate length of the device. Additionally, a methodology is presented, which enables reliable and reproducible manufacturing of reference samples with engineered sheet-specific indent variations at nominal etch processing. Such samples are ideal candidates for evaluating metrology solutions with minimal destructive reference metrology costs. Two strategies, single parameter and sheet-specific indent monitoring are discussed, and it was found that the addition of spectroscopic information acquired by Spectral Interferometry improved both optical metrology solutions. In addition to improving the match to references for single parameter indent monitoring, excellent sheet-specific indent results can be delivered
Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the threshold voltage (VT) and yield. Metrology challenges for obtaining these metrics arise from increasingly dense arrays coupled with both high aspect ratios, high numbers of correlated parameters, and increasingly complex 3D geometries. Large area metrology structures can be used for 3D parameters’ process monitoring through techniques such as scatterometry and xray diffraction (XRD) which deliver averaged results over that area, but variation impacting specific devices cannot currently be understood without destructive cross-section. Prior work to characterize the dimensions of these GAA devices has primarily featured optical metrology, X-ray metrology, and critical-dimension scanning electron microscopy (CDSEM), but these techniques have their own challenges at the critical process points. Atomic force microscopy (AFM) had not been utilized due to the aspect ratios and small trench widths which were inaccessible to conventional techniques. However, due to recent advances in scanning and novel probe technologies, AFM is well-suited now to solve these local, three-dimensional challenges. Through this study, we demonstrate AFM characterization of a key process point in the GAA process flow for multiple structures with varying channel lengths, after epitaxial (epi) growth along the Si sidewall. The AFM scan results are compared to CDSEM images for top-down corroboration of topography and to other reference metrology for height correlation. The impact of measured variations in epi height to device performance is also reviewed.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.
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