In typical DRIE processes, the etch rate variation across the wafer increases with pattern density, severely limiting the pattern densities that can be used at a specified etch rate tolerance. Here, we present a scheme for including uniformity-improving dummy structures in the etch mask layout that enable the use of high-density patterns in many DRIE process types. The dummy structures take up relatively little space in the layout and reduce the total etch rate variation of a 35% etchable area pattern by 66% while maintaining a high etch rate.
KEYWORDS: Etching, Deep reactive ion etching, Semiconducting wafers, Fluorine, Silicon, Reactive ion etching, Diffusion, Scanning electron microscopy, Ions, Microelectromechanical systems
Knowledge of the magnitude and characteristic length scales of chip-scale process variations due to varying substrate pattern density is essential if compensation measures, such as incorporation of dummy structures, are to be taken during mask layout. Effects of variations in local pattern density on a deep reactive ion etch (DRIE) process have been investigated, and a decrease of the etch rate with increasing local pattern density within a characteristic radius of approximately 4.5 mm has been found. Analytical and numerical calculations confirm the existence of a similar depletion radius under the experimental conditions used.
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