This paper presents a methodology to optimize standard cells and other small IP for manufacturability. The optimization is based on an evolutionary machine learning algorithm. This algorithm creates variants of a starting cell by randomly selecting and moving edges, and selects the best variant based on a scoring methodology for the next set of iterations. The opportunity for such an algorithm arises from the complexity of advanced node design rules, where multiple rules compete and have to be optimized simultaneously across multiple mask layers. Doing this process manually is a lengthy and highly iterative process and most often leaves DFM opportunities on the table. The selector in the algorithm is a combination of MAS/DRC rule-based checks, and a holistic multi-layer lithographic process window metric. Specifically library standard cells can be optimized for DFM scores and printability within a very short time frame.
Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.
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