Mr. Kenichi Kobayashi Profile

Kenichi Kobayashi

at Canon Inc

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Publications (1)

Proceedings Article | 16 September 2022 Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Kenichi Kobayashi, Hirotoshi Torii, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Jin Choi, Teresa Estrada

Proceedings Volume 12325, 1232504 (2022) https://doi.org/10.1117/12.2640651

KEYWORDS: Photomasks, Semiconductors, Optical lithography, Manufacturing, Semiconducting wafers, Etching, Molybdenum, Logic, Helium

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Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

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