Proceedings Article | 16 April 2014
KEYWORDS: Modulators, Double positive medium, Transistors, Sensors, Video, Image sensors, Digital electronics, Analog electronics, CMOS sensors, Standards development
A delta-sigma, or sigma-delta, analog-to-digital converter (ADC) comprises both a modulator, which implements oversampling and noise shaping, and a decimator, which implements low-pass filtering and downsampling. Whereas these ADCs are ubiquitous in audio applications, their usage in video applications is emerging. Because of oversampling, it is preferable to integrate delta-sigma ADCs at the pixel level of megapixel video sensors. Moreover, with pixel-level applications, area usage per ADC is much more important than with chip-level applications, where there is only one or a few ADCs per chip. Recently, a small-area decimator was presented that is suitable for pixel-level applications. However, though the pixel-level design is small enough for invisible-band video sensors, it is too large for visible-band ones. As shown here, nanoscale CMOS processes offer a solution to this problem. Given constant specifications, small-area decimators are designed, simulated, and laid out, full custom, for 180, 130, and 65nm standard CMOS processes. Area usage of the whole decimator is analyzed to establish a roadmap for the design and demonstrate that it could be competitive compared to other digital pixel sensors, based on Nyquist-rate ADCs, that are being commercialized.
