Mr. Didier Dabernat Profile

Didier Dabernat

at STMicroelectronics SA

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Proceedings Article | 20 March 2020 Paper

Mitigating gain, effort and cost for EOW overlay control

Olivier Mermet, Maxime Gatefait, Didier Dabernat, Florent Dettoni, Benjamin Duclaux, Bertrand Le-Gratiet

Proceedings Volume 11325, 113251W (2020) https://doi.org/10.1117/12.2548308

KEYWORDS: Etching, Semiconducting wafers, Scanners, Overlay metrology, Contamination, Lithography, Plasma

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Advanced nodes require tighter and tighter overlay control to secure products yield. Market like automotive one are even more demanding on “overlay reliability” till the extreme edge of wafers. High order models including Correction per Exposure capabilities are now introduced on the most critical immersion layers to put extra correction on the edge of wafers scanner fields. To ensure a correction model able to bring back these fields under overlay specification, the understanding of key process/equipment parameters to be put under control is needed. In this paper, choices done in term of overlay and Run to Run model will be discussed. On tools aspects, scanner table clean frequency impact and etch chambers variability will be addressed. In addition, etch recipe can modulate this etch chamber effect. The paper will conclude on the compromise to face in order to better correct and control overlay at the Edge of Wafer with the current Litho/Etch tools capabilities and R2R model strategy, at an acceptable cost (tool efficiency) and effort (rework, R2R complexity, …)

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