Mr. Daehan Han Profile

Daehan Han

at SAMSUNG Electronics Co Ltd

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Author

Publications (5)

Proceedings Article | 16 March 2016 Paper

The new analysis method of PWQ in the DRAM pattern

Daehan Han, Jinman Chang, Taeheon Kim, Kyusun Lee, Yonghyeon Kim, Jinyoung Kang, Aeran Hong, Bumjin Choi, Joosung Lee, Hyoung Jun Kim, Kweonjae Lee, Hyoungsun Hong, Gyoyoung Jin

Proceedings Volume 9781, 97810R (2016) https://doi.org/10.1117/12.2218414

KEYWORDS: Inspection, Quantitative analysis, Defect detection, Image processing, Solids, Design for manufacturing, Design for manufacturability, Manufacturing, Semiconducting wafers, Error analysis, Critical dimension metrology, Double patterning technology, Metrology

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In a sub 2Xnm node process, the feedback of pattern weak points is more and more significant. Therefore, it is very important to extract the systemic defect in Double Patterning Technology(DPT), however, it is impossible to predict exact systemic defect at the recent photo simulation tool.[1] Therefore, the method of Process Window Qualification (PWQ) is very serious and essential these days.

Conventional PWQ methods are die to die image comparison by using an e-beam or bright field machine. Results are evaluated by the person, who reviews the images, in some cases. However, conventional die to die comparison method has critical problem. If reference die and comparison die have same problem, such as both of dies have pattern problems, the issue patterns are not detected by current defect detecting approach. Aside from the inspection accuracy, reviewing the wafer requires much effort and time to justify the genuine issue patterns. Therefore, our company adopts die to data based matching PWQ method that is using NGR machine. The main features of the NGR are as follows. First, die to data based matching, second High speed, finally massive data were used for evaluation of pattern inspection.[2] Even though our die to data based matching PWQ method measures the mass data, our margin decision process is based on image shape. Therefore, it has some significant problems.

First, because of the long analysis time, the developing period of new device is increased. Moreover, because of the limitation of resources, it may not examine the full chip area. Consequently, the result of PWQ weak points cannot represent the all the possible defects. Finally, since the PWQ margin is not decided by the mathematical value, to make the solid definition of killing defect is impossible.

To overcome these problems, we introduce a statistical values base process window qualification method that increases the accuracy of process margin and reduces the review time. Therefore, it is possible to see the genuine margin of the critical pattern issue which we cannot see on our conventional PWQ inspection; hence we can enhance the accuracy of PWQ margin.

Proceedings Article | 19 March 2015 Paper

The analysis method of the DRAM cell pattern hotspot

Kyusun Lee, Kweonjae Lee, Jinman Chang, Taeheon Kim, Daehan Han, Aeran Hong, Yonghyeon Kim, Jinyoung Kang, Bumjin Choi, Joosung Lee, Jooyoung Lee, Hyeongsun Hong, Kyupil Lee, Gyoyoung Jin

Proceedings Volume 9424, 94241D (2015) https://doi.org/10.1117/12.2084992

KEYWORDS: Semiconducting wafers, Inspection, Composites, Scanning electron microscopy, Reticles, Double patterning technology, Sensors, Optical lithography, Etching, Line edge roughness

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Proceedings Article | 18 March 2015 Paper

The cell pattern correction through design-based metrology

Yonghyeon Kim, Kweonjae Lee, Jinman Chang, Taeheon Kim, Daehan Han, Kyusun Lee, Aeran Hong, Jinyoung Kang, Bumjin Choi, Joosung Lee, Kyehee Yeom, Jooyoung Lee, Hyeongsun Hong, Kyupil Lee, Gyoyoung Jin

Proceedings Volume 9427, 942713 (2015) https://doi.org/10.1117/12.2085004

KEYWORDS: Bridges, Overlay metrology, Inspection, Composites, Metrology, Error analysis, Semiconducting wafers, Optical lithography, Lithography, Defect inspection

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Proceedings Article | 15 March 2012 Paper

A study of pattern variability for device performance

Tae-Heon Kim, Dae-Han Han, Ae-Ran Hong, Yong-Hyeon Kim, Joo-Sung Lee, Yun-Hye Chu, Kweon-Jae Lee, Yong-Jik Park

Proceedings Volume 8327, 83270Y (2012) https://doi.org/10.1117/12.915934

KEYWORDS: Transistors, Optical proximity correction, Critical dimension metrology, Lithography, Semiconducting wafers, Design for manufacturing, Etching, Image classification, Photomasks, Manufacturing

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Proceedings Article | 5 April 2011 Paper

Applications of DBV (design-based verification) for steep ramp-up manufacture

Tae Heon Kim, Dae-Han Han, Yong-Hyeon Kim, Min-Chul Han, Hong-Ji Lee, Ae-Ran Hong, Yoon-Min Kim, In-Ho Nam, Yong-Jik Park, Kyung-Seok Oh

Proceedings Volume 7974, 79740Q (2011) https://doi.org/10.1117/12.879033

KEYWORDS: Critical dimension metrology, Inspection, Semiconducting wafers, Manufacturing, Transistors, Etching, Lithography, Control systems, Design for manufacturability, Photomasks

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