A novel 3300V conductivity modulation enhanced planar gate IGBT (CE-IGBT) with P-type Schottky contact and partial N-type buried layer is proposed. The proposed CE-IGBT features a P-type Schottky contact between the P-base region and emitter metal as well as a partial highly-doped N-type buried layer located in the P-base region. The Schottky contact forms a hole barrier by increasing the potential of the P-base region and the N-type buried layer suppresses the hole flowing above it. The simulation results show that compared with the conventional planar gate IGBT (Con-IGBT), the proposed CE-IGBT not only reduces the on-state voltage drop (Vceon) but also improves the trade-off relationship between the Vceon and turn-off power loss (Eoff). Compared with the Con-IGBT, the Vceon of the CE-IGBT with same P-base doping concentration is reduced by 32.7%, and the CE-IGBT pro with same threshold voltage (Vth) is reduced by 30.9%. At same Vceon of 2.65 V, compared with the Con-IGBT, the Eoff of the CE-IGBT and CE-IGBT pro is reduced by 37.3% and 34.9%, respectively. Moreover, the proposed device demonstrates good reverse biased safe operating area (RBSOA).
Single photon flash light detection and ranging (LiDAR), which is based on Geiger Mode avalanche photodiode (GMAPD) array, enables superior sensitivity and detection range to obtaining depth information. The Flash LiDAR captures an entire 3D image by single laser pulse, much faster than conventional LiDAR based on the scanning of a single detector over the scene. In conventional advanced driver assistant systems (ADAS), closer and weaker reflections caused by the environmental factors will cause misidentification. Furthermore, power dissipation and limited pixel size are enormous challenges for Readout Integrated Circuit (ROIC) design. The paper proposes the design of ROIC with Multi-Echo Detection for 128×32 GM-APD Array. The pixel includes active quenching and reset circuit of GM-APD, and embedded 11-bit Time to Digital Converter (TDC) offers precise distance resolution by Time of Flight (TOF) measurement. The proposed ROIC is designed with 0.18μm CMOS process. Due to shared DFFs by TDC and shift register, 90μm pixel pitch is realized with Multi-Echo Detection function. Global clock gating(GCG) and shift clock gating(SCG) techniques bring the power dissipation down to 464.6mW.
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