Paper
23 October 2000 Novel resource optimization approach for yield learning
Ramakrishna Akella
Author Affiliations +
Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404887
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
In this paper, we describe a new integrated framework for yield learning, based on linking traditional inspection sampling, and current ADC classification procedures. The elements of a yield learning cycle, and the drivers, are identified. We then review results concerning integrated inspection-classification/review procedures that reduce yield loss detection; these incorporate new optimized control charts that incorporate killer and non-killer defect types, with classification errors, as well as integrated queuing-hypothesis testing approaches combining resource management and excursion detection. We briefly touch upon tactical approaches for achieving source isolation and prioritizing source isolation and root cause analysis.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ramakrishna Akella "Novel resource optimization approach for yield learning", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404887
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Cited by 1 scholarly publication.
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KEYWORDS
Inspection

Semiconducting wafers

Wafer inspection

Signal detection

Defect inspection

Yield improvement

Adaptive control

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