In-line wafer inspection using 100-megapixel-per-second digital image processing technology

Gary Dickerson; Rick P. Wallace

doi:10.1117/12.44469

1 July 1991 In-line wafer inspection using 100-megapixel-per-second digital image processing technology

Gary Dickerson, Rick P. Wallace

Proceedings Volume 1464, Integrated Circuit Metrology, Inspection, and Process Control V; (1991) https://doi.org/10.1117/12.44469
Event: Microlithography, 1991, San Jose, CA, United States

Abstract

Reducing defect density to an acceptable level is one of the most challenging problems in manufacturing 16 Mbit DRAMs. To implement an effective defect elimination strategy, it is necessary to have both a defect inspection system that can find all critical defects on the wafer and a strong defect reduction methodology. The optimum system would provide the highest sensitivity along with sufficient inspection speed to fit a majority of inspection applications. This paper describes a new system, the KLA 2110, designed to meet production requirements for speed, sensitivity, and ease of use. The system provides 0.25 micrometers sensitivity with image processing rates 100 times faster than previous generation digital image processing technology.

Citation Download Citation

Gary Dickerson and Rick P. Wallace "In-line wafer inspection using 100-megapixel-per-second digital image processing technology", Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); https://doi.org/10.1117/12.44469

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