Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm
technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer
formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of
SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires
precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In
our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the
results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching
performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with
mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We
reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is
capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern
pitch and stack layer thickness on lateral etch results have been studied by simulation.
KEYWORDS: Low pressure chemical vapor deposition, Plasma enhanced chemical vapor deposition, Scanning electron microscopy, Silicon, Ions, Field effect transistors, Transmission electron microscopy, Process modeling, Deposition processes, Computer simulations
The inner spacer process is a critical step in gate-all-around (GAA) nanosheet FET device fabrication and SiN is the most common material to be deposited after the indentation of the SiGe layer of alternative Si/SiGe layer structure. This gap filling process demands for highly uniform growth in order to minimize transistor variability, the lateral open feature of the indentation brings new challenges to conventional deposition technologies such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). In this work, we propose an analytical model of SiN deposition to predict the profile evolution of both LPCVD and PECVD, which can help process tuning and understand the influence of the multi-layer geometry and process condition on inner spacer growth performance in a more efficient and economical way. Experimental results reveal that the filling effect of LPCVD is significantly better than that of PECVD, simulation results also validate this. We also compare simulations with experiments, by comparing the model output with original SEM image, satisfactory matching between the two profiles demonstrates the validity of this model. Moreover, we set the SiGe layer thickness to be 10nm, 20nm and 30nm, and SiGe indentation as 10nm, 30nm and 50nm. Simulation reveals that the geometry has significant impact on the deposition performance. When the indentation is less than 10nm, both LPCVD and PECVD exhibit good SiN coverage. However, when indentation is deepened from 10nm to 30nm and 50nm, for PECVD, void firstly forms in 10nm thick SiGe layer and the necking effect tends to form larger void in 20nm and 30nm thick SiGe layers. For LPCVD, however, SiN grows more uniformly within and outside the cavity, and only very narrow gaps form in the cavity.
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