Resist poisoning is one of the key issues linked to low-k dielectric and copper integration. This phenomenon tends to be amplified in dual damascene architecture, where both processes and materials are incriminated, especially when porous low-k dielectrics are integrated. In this paper we present and implement the dose to clear compensation method, easily undertaken with standard lithography and metrology tools, to evaluate quantitatively 248 and 193nm photo-resist poisoning on both MSQ and porous MSQ substrates. We show the amplification of resist poisoning due to the reservoir effect in porous MSQ, and address the role of the porosity in the phenomenon. We demonstrate the efficiency of the method in evaluating hard masks compatibility, wet and dry stripping processes, and its ability in screening photo-resist in term of poisoning sensitivity.
To print subwavelength dimension features in optical lithography, one must correct significant Optical Proximity Effects as well as some other process outcomes. Nowadays, different firms propose to Silicon Industry Optical Proximity Correction (OPC) software. This software may be either Rule-based or Model-based or a mixed of both methods. To have the most judicious choice to acquire one of them, we prepare a procedure of evaluation with both mask manufacturing interest and Silicon process concern. The first part of the work is a technical study. We evaluate the OPC generation step in terms of speed, used memory an size evolution of the databases. We add a qualitative evaluation of the correction quality after lithography simulation. The second part of the work is the manufacturability evaluation. The results of the layout, produced by suppliers are analyzed and compared in term of mask complexity, mask resolution and anomalies generated.
In this study, we focus on mask manufacturing contribution on 248 nm and 193 nm lithography performances. The masks are manufactured at DPI using both E-beam/laser writing technologies (e-beam/laser) and two etching processes (wet/dry). Masks are optimized for 150 nm node at wafer scale, neither RET not tuning are used, despite of this, we obtain excellent and unexpected results for inferior nodes which highlight the robustness of the manufacturing mask process being used.
In this study, we focus on mask manufacturing contribution on 248nm & 193nm lithography performances. The masks are manufactured at DPI using both E-beam/Laser writing technologies (e-beam/laser) and two etching processes (Wet/Dry). Masks are optimized for 150nm node at wafer scale, neither RET nor tuning are used, despite of this, we obtain excellent and unexpected results for inferior nodes which highlight the robustness of the manufacturing mask processes being used.
Laurent Pain, Yorick Trouiller, Alexandra Barberet, O. Guirimand, Gilles Fanget, N. Martin, Yves Quere, M. Nier, Emile Lajoinie, Didier Louis, Michel Heitzmann, P. Scheiblin, A. Toffoli
193 nm lithography is expected today to be an emerging solution for the development and the production of future integrated circuits based on sub 150 nm design rules. However the characterization and the evaluation of these tools require a lot of effort due to the 193 nm resist behavior during SEM observations. This paper presents the process flow chart to allow the evaluation of a ASM-L 5500/900 193 nm scanner by electrical measurement and the stack used for this study. After the validation of this flow chart, this work gives an overview of the ASM-L 5500/900 performances.
The goal of this paper is to understand the optical phenomena at dielectric levels (contact, local interconnect, via and damascene line levels). The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective Coating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resist and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this stack: by extending the Perot-Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters (metal, oxide thickness, resist thickness, BARC absorbency). Experimentally CD variations for damascene line level on 0.18 micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments.
The goal of this paper is to understand the optical phenomena at dielectric levels. The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective COating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resists and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this tack: by extending the Perot/Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters. Experimentally CD variation for Damascene line level on 0.18micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments. The main conclusions are: (1) Depending on your dielectric deposition and CMP processes, if resist thickness is controlled, a standard BARC process used for the gate is adapted to remove oxide thickness variation influence providing the optimized resist thickness is used. (2) If both resist thickness and dielectric thickness are uncontrolled, a more absorbent BARC is required.
BARC technology, originally developed for gate level has now to be applied to interconnection one's. Requirements for dielectric interconnection levels are different from gate level. In the case of gate level ARC has to minimize reflectivity at resist/substrate interface due to notching and resist swing curve effects. Whereas ARC for interconnections has to minimize reflectivity variation at resist/substrate interface due to swing curve effect in the dielectric layer. For interconnections, ARC must be as absorbent as possible at stepper exposure wavelength, and two ways are foreseen: ARC layer with high k value at 248 nm, and ARC layer with high thickness. For a reflectivity variation minimum criteria, we can find a couple values (k, minimum thickness). Experiments give us for a reflectivity variation below 5% the following couples: (k equals 0.7, 1200 Angstrom thickness) and (k equals 1.1, 850 Angstrom). In this paper we describe different applications of SiOxNy for interconnection levels: via, contact and damascene line level. Improvements depending of the SiOxNy thickness are seen in CD dispersion. To conclude SiOxNy ARC can be used for interconnection levels, and its performances depends on ARC couple values (k, thickness).
BARC technology, originally developed for gate level has now to be applied to interconnection one's. Requirements for dielectric interconnection levels are different from gate level. In the case of gate level ARC has to minimize reflectivity at resist/substrate interface due to notching and resist swing curve effects. Whereas ARC for interconnections has to minimize reflectivity variation at resist/substrate interface due to swing curve effect in the dielectric layer. For interconnection, ARC must be as absorbent as possible at stepper exposure wavelength, and two ways are foreseen: ARC layer with high k value at 248 nm, and ARC layer with high thickness. For a reflectivity variation minimum criteria, we can find a couple values (k, minimum thickness). Experiments give us for a reflectivity variation below 5% the following couples: (k equals 0.7, 1200 angstroms thickness) and (k equals 1.1, 850 angstroms). In this paper we describe different applications of SiOxNy for interconnection levels: via, contact and damascene line level. Improvements depending of the SiOxNy thickness are seen in CD dispersion. To conclude SiOxNy ARC can be used for interconnection levels, and its performance depends on ARC couple values (k, thickness).
The phase shift mask (PSM) is a key emerging technology thought to be extending 248 nm lithography. In this paper, we describe the lithographic performances of Shipley UV5 photoresist on SiOxNy Bottom Anti Reflective coating (BARC), using alternating PSM and ASM/90 Deep-UV stepper. Results on 0.18 micrometer design rules are presented: lithographic performances, comparison between PSM and binary mask, sub 0.18 micrometer performances ({1}) and the ultimate resolution of this technology are reported. To conclude we demonstrated the 0.18 micrometer lithography feasibility with alternating mask and KrF stepper, and showed that all the necessary tools are today available to achieve such goals.
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