Mr. Ylber Hasani Profile

Ylber Hasani

at AIT Austrian Institute of Technology GmbH

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Proceedings Article | 14 February 2015 Paper

FPGA based image processing for optical surface inspection with real time constraints

Ylber Hasani, Ernst Bodenstorfer, Jörg Brodersen, Konrad Mayer

Proceedings Volume 9445, 94450P (2015) https://doi.org/10.1117/12.2181432

KEYWORDS: Digital signal processing, Field programmable gate arrays, Image processing, Cameras, Clocks, Inspection, Optical inspection, Signal processing, Image resolution, Interfaces

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Today, high-quality printing products like banknotes, stamps, or vouchers, are automatically checked by optical surface inspection systems. In a typical optical surface inspection system, several digital cameras acquire the printing products with fine resolution from different viewing angles and at multiple wavelengths of the visible and also near infrared spectrum of light. The cameras deliver data streams with a huge amount of image data that have to be processed by an image processing system in real time. Due to the printing industry’s demand for higher throughput together with the necessity to check finer details of the print and its security features, the data rates to be processed tend to explode. In this contribution, a solution is proposed, where the image processing load is distributed between FPGAs and digital signal processors (DSPs) in such a way that the strengths of both technologies can be exploited. The focus lies upon the implementation of image processing algorithms in an FPGA and its advantages. In the presented application, FPGAbased image-preprocessing enables real-time implementation of an optical color surface inspection system with a spatial resolution of 100 μm and for object speeds over 10 m/s. For the implementation of image processing algorithms in the FPGA, pipeline parallelism with clock frequencies up to 150 MHz together with spatial parallelism based on multiple instantiations of modules for parallel processing of multiple data streams are exploited for the processing of image data of two cameras and three color channels. Due to their flexibility and their fast response times, it is shown that FPGAs are ideally suited for realizing a configurable all-digital PLL for the processing of camera line-trigger signals with frequencies about 100 kHz, using pure synchronous digital circuit design.

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