Future robots and autonomous vehicles require compact low-cost Laser Detection and Ranging (LADAR) systems for
autonomous navigation. Army Research Laboratory (ARL) had recently demonstrated a brass-board short-range eye-safe
MEMS scanning LADAR system for robotic applications. Boeing Spectrolab is doing a tech-transfer (CRADA) of this
system and has built a compact MEMS scanning LADAR system with additional improvements in receiver sensitivity,
laser system, and data processing system. Improved system sensitivity, low-cost, miniaturization, and low power
consumption are the main goals for the commercialization of this LADAR system. The receiver sensitivity has been
improved by 2x using large-area InGaAs PIN detectors with low-noise amplifiers. The FPGA code has been updated to
extend the range to 50 meters and detect up to 3 targets per pixel. Range accuracy has been improved through the
implementation of an optical T-Zero input line. A compact commercially available erbium fiber laser operating at 1550
nm wavelength is used as a transmitter, thus reducing the size of the LADAR system considerably from the ARL brassboard
system. The computer interface has been consolidated to allow image data and configuration data (configuration
settings and system status) to pass through a single Ethernet port. In this presentation we will discuss the system
architecture and future improvements to receiver sensitivity using avalanche photodiodes.
KEYWORDS: LIDAR, Mirrors, Field programmable gate arrays, Sensors, Receivers, Transmitters, Data acquisition, Signal to noise ratio, Microelectromechanical systems, Robots
The Army Research Laboratory (ARL) is researching a short-range ladar imager for navigation, obstacle/collision
avoidance, and target detection/identification on small unmanned ground vehicles (UGV).To date, commercial UGV
ladars have been flawed by one or more factors including low pixelization, insufficient range or range resolution, image
artifacts, no daylight operation, large size, high power consumption, and high cost. ARL built a breadboard ladar based
on a newly developed but commercially available micro-electro-mechanical system (MEMS) mirror coupled to a lowcost
pulsed Erbium fiber laser transmitter that largely addresses these problems. Last year we integrated the ladar and
associated control software on an iRobot PackBot and distributed the ladar imagery data via the PackBot's computer
network. The un-tethered PackBot was driven through an indoor obstacle course while displaying the ladar data realtime
on a remote laptop computer over a wireless link. We later conducted additional driving experiments in cluttered
outdoor environments. This year ARL partnered with General Dynamics Robotics Systems to start construction of a
brass board ladar design. This paper will discuss refinements and rebuild of the various subsystems including the
transmitter and receiver module, the data acquisition and data processing board, and software that will lead to a more
compact, lower cost, and better performing ladar. The current ladar breadboard has a 5-6 Hz frame rate, an image size of
256 (h) × 128 (v) pixels, a 60° × 30° field of regard, 20 m range, eyesafe operation, and 40 cm range resolution (with
provisions for super-resolution or accuracy).
The Army Research Laboratory (ARL) is researching a short-range ladar imager for small unmanned ground vehicles for
navigation, obstacle/collision avoidance, and target detection and identification. To date, commercial ladars for this
application have been flawed by one or more factors including, low pixelization, insufficient range or range resolution,
image artifacts, no daylight operation, large size, high power consumption, and high cost. In the prior year we conceived
a scanned ladar design based on a newly developed but commercial MEMS mirror and a pulsed Erbium fiber laser. We
initiated construction, and performed in-lab tests that validated the basic ladar architecture. This year we improved the
transmitter and receiver modules and successfully tested a new
low-cost and compact Erbium laser candidate. We further
developed the existing software to allow adjustment of operating parameters on-the-fly and display of the imaged data in
real-time. For our most significant achievement we mounted the ladar on an iRobot PackBot and wrote software to
integrate PackBot and ladar control signals and ladar imagery on the PackBot's computer network. We recently remotely
drove the PackBot over an inlab obstacle course while displaying the ladar data real-time over a wireless link. The ladar
has a 5-6 Hz frame rate, an image size of 256 (h) × 128 (v) pixels, a 60° x 30° field of regard, 20 m range, eyesafe
operation, and 40 cm range resolution (with provisions for super-resolution or accuracy). This paper will describe the
ladar design and update progress in its development and performance.
The Army Research Laboratory (ARL) is researching a short-range ladar imager for small unmanned ground vehicles for
navigation, obstacle/collision avoidance, and target detection and identification. To date, commercial ladars for this
application have been flawed by one or more factors including, low pixelization, insufficient range or range resolution,
image artifacts, no daylight operation, large size, high power consumption, and high cost. The ARL conceived a
scanned ladar design based on a newly developed but commercial MEMS mirror and a pulsed Erbium fiber laser. The
desired performance includes a 6 Hz frame rate, an image size of 256 (h) × 128 (v) pixels, a 60° × 30° field of regard, 20
m range, eyesafe operation, and 40 cm range resolution (with provisions for super-resolution or accuracy). The ladar will
be integrated on an iRobot PackBot. To date, we have built and tested the transceiver when mounted in the PackBot armmounted
sensor head. All other electronics including the data acquisition and signal processing board, the power
distribution board, and other smaller ancillary boards are built and operating. We are now operating the ladar and
working on software development. This paper will describe the ladar design and progress in its development and
performance.
Shipboard infrared search and track (IRST) systems can detect sea-skimming anti-ship missiles at long ranges, but cannot distinguish missiles from slowly moving false targets and clutter. In a joint Army-Navy program, the Army Research Laboratory (ARL) is developing a ladar to provide unambiguous range and velocity measurements of targets detected by the distributed aperture system (DAS) IRST system being developed by the Naval Research Laboratory (NRL) sponsored by the Office of Naval Research (ONR). By using the ladar's range and velocity data, false alarms and clutter objects will be distinguished from incoming missiles. Because the ladar uses an array receiver, it can also provide three-dimensional (3-D) imagery of potential threats at closer ranges in support of the force protection/situational awareness mission. The ladar development is being accomplished in two phases. In Phase I, ARL designed, built, and reported on an initial breadboard ladar for proof-of-principle static platform field tests. In Phase II, ARL was tasked to design, and test an advanced breadboard ladar that corrected various shortcomings in the transmitter optics and receiver electronics and improved the signal processing and display code. The advanced breadboard will include a high power laser source utilizing a long pulse erbium amplifier built under contract. Because award of the contract for the erbium amplifier was delayed, final assembly of the advanced ladar is delayed. In the course of this year's work we built a "research receiver" to facilitate design revisions, and when combined with a low-power laser, enabled us to demonstrate the viability of the components and subsystems comprising the advanced ladar.
We describe a 2-D fully differential Readout Integrated Circuit (ROIC) designed to convert the photocurrents from an array of differential metal-semiconductor-metal (MSM) detectors into voltage signals suitable for digitization and post processing. The 2-D MSM array and CMOS ROIC are designed to function as a front-end module for an amplitude modulated/continuous time AM/CW 3-D Ladar imager under development at the Army Research Laboratory. One important aspect of our ROIC design is scalability. Within reasonable power consumption and photodetector size constraints, the ROIC architecture presented here scales up linearly without compromising complexity. The other key feature of our ROIC design is the mitigation of local oscillator coupling. In our ladar imaging application, the signal demodulation process that takes place in the MSM detectors introduces parasitic radio frequency (rf) currents that can be 4 to 5 orders of magnitude greater than the signal of interest. We present a fully-differential photodetector architecture and a circuit level solution to reduce the parasitic effect. As a proof of principle we have fabricated a 0.18 μm CMOS 32x16 fully differential ROIC with an array of 32 correlated double sampling (cds) capacitive transimpedance amplifiers (CTIAs), and a custom printed circuit board equipped to verify the test chip functionality. In this paper we discuss the fully differential IC design architecture and implementation and present the future testing strategy.
Shipboard infrared search and track (IRST) systems can detect sea-skimming anti-ship missiles at long ranges. Since IRST systems cannot measure range and line-of-sight velocity, they have difficulty distinguishing missiles from slowly moving false targets and clutter. In a joint Army-Navy program, the Army Research Laboratory (ARL) is developing a chirped amplitude modulation ladar to provide range and velocity measurements for tracking of targets handed over to it by the distributed aperture system IRST (DAS-IRST) under development at the Naval Research Laboratory (NRL) under Office of Naval Research (ONR) sponsorship. By using an array receiver based on Intevac Inc.'s Electron Bombarded Active Pixel Sensor (EBAPS) operating near 1.5 μm wavelength, ARL's ladar also provides 3D imagery of potential threats in support of the force protection mission. In Phase I, ARL designed and built a breadboard ladar system for proof-of-principle static platform field tests. In Phase II, ARL is improving the ladar system to process and display 3D imagery and range-Doppler plots in near real-time, to re-register frames in near real-time to compensate for platform and target lateral motions during data acquisition, and to operate with better quality EBAPS tubes with higher quantum efficiency and better response spatial uniformity. The chirped AM ladar theory, breadboard design, performance model results, and initial breadboard preliminary test results were presented last year at this conference. This paper presents the results of tests at the Navy's Chesapeake Bay Detachment facility. The improvements to the ladar breadboard since last year are also presented.
An alternative, class AB configuration of a proven class A readout cell for active/passive imaging systems is presented. Comparison between the two approaches shows that class AB circuit lowers power consumption and reduces noise by a factor of 3 while using nearly equal chip area. On the other hand, class AB has lower bandwidth because it operates at lower bias currents. A 0.5μm CMOS test chip that includes both types of readout circuits has been designed, fabricated and is currently being tested. Simulation results, using readout circuits from this test chip, are used to compare the two configurations.
Shipboard infrared search and track (IRST) systems can detect sea-skimming, anti-ship missiles at long ranges. Since IRST systems cannot measure range and line-of-sight (LOS) velocity, they have difficulty distinguishing missiles from false targets and clutter. In a joint Army-Navy program, the Army Research Laboratory (ARL) is developing a ladar based on the chirped amplitude modulation (AM) technique to provide range and velocity measurements of potential targets handed-over by the distributed aperture system - IRST (DAS-IRST) being developed by the Naval Research Laboratory (NRL) and sponsored by the Office of Naval Research (ONR). Using the ladar's range and velocity data, false alarms and clutter will be eliminated, and valid missile targets' tracks will be updated. By using an array receiver, ARL's ladar will also provide 3D imagery of potential threats for force protection/situational awareness. The concept of operation, the Phase I breadboard ladar design and performance model results, and the Phase I breadboard ladar development program were presented in paper 5413-16 at last year's symposium. This paper will present updated design and performance model results, as well as recent laboratory and field test results for the Phase I breadboard ladar. Implications of the Phase I program results on the design, development, and testing of the Phase II brassboard ladar will also be discussed.
The Army Research Laboratory is researching system architectures and components required to build a 32x32 pixel scannerless ladar breadboard. The 32x32 pixel architecture achieves ranging based on a frequency modulation/continuous wave (FM/cw) technique implemented by directly amplitude modulating a near-IR diode laser transmitter with a radio frequency (RF) subcarrier that is linearly frequency modulated (i.e. chirped amplitude modulation). The backscattered light is focused onto an array of metal-semiconductor-metal (MSM) detectors where it is detected and mixed with a delayed replica of the laser modulation signal that modulates the responsivity of each detector. The output of each detector is an intermediate frequency (IF) signal (a product of the mixing process) whose frequency is proportional to the target range. Pixel read-out is achieved using code division multiple access techniques as opposed to the usual time-multiplexed techniques to attain high effective frame rates. The raw data is captured with analog-to-digital converters and fed into a PC to demux the pixel data, compute the target ranges, and display the imagery. Last year we demonstrated system proof-of-principle for the first time and displayed an image of a scene collected in the lab that was somewhat corrupted by pixel-to-pixel cross-talk. This year we report on system modifications that reduced pixel-to-pixel cross-talk and new hardware and display codes that enable near real-time stereo display of imagery on the ladar's control computer. The results of imaging tests in the laboratory will also be presented.
Shipboard infrared search and track (IRST) systems can detect sea-skimming anti-ship missiles at long ranges. Since IRST systems cannot measure range and velocity, they have difficulty distinguishing missiles from slowly moving false targets and clutter. ARL is developing a ladar based on its patented chirped amplitude modulation (AM) technique to provide unambiguous range and velocity measurements of targets handed over to it by the IRST. Using the ladar's range and velocity data, false alarms and clutter objects will be distinguished from valid targets. If the target is valid, it's angular location, range, and velocity, will be used to update the target track until remediation has been effected. By using an array receiver, ARL's ladar can also provide 3D imagery of potential threats in support of force protection. The ladar development program will be accomplished in two phases. In Phase I, currently in progress, ARL is designing and building a breadboard ladar test system for proof-of-principle static platform field tests. In Phase II, ARL will build a brassboard ladar test system that will meet operational goals in shipboard testing against realistic targets. The principles of operation for the chirped AM ladar for range and velocity measurements, the ladar performance model, and the top-level design for the Phase I breadboard are presented in this paper.
We are engaged in research of readout techniques and development of readout integrated circuits for active and active/passive imaging systems under development at the Army Research Laboratory. Here we report a readout integrated circuit chip designed for ARL's FM/cw line-imaging ladar. The readout chip consists of two 1 x 8 element arrays of high-gain amplifiers that convert the input photocurrent signal to a voltage signal appropriate for digitization. Each amplifier consists of a transimpedance input stage op amp followed by a voltage-gain op amp and output buffer. The input transimpedance stage is a CMOS operational amplifier designed for a transimpedance gain of almost 1 MΩ. The voltage amplifier of stage two, also an operational amplifier, is designed to provide additional gain of about 150. Test chips have been fabricated and are being tested. The initial measured transimpedance gain of the entire amplifier cell is 130 MΩ. We discuss the chip design, physical layout, and initial performance test results.
A high-bandwidth, free-space integrated optoelectronic interconnect system was built for high-density, parallel data transmission and processing. Substrate-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) arrays and photodetector arrays, both driven by complimentary metal- oxide-semiconductor (CMOS) circuitry, were employed as a transmitter and receiver. We designed, fabricated, hybridized, and packaged the VCSEL transmitter and photoreceiver arrays. Data rates above 1 Gbs for each channel on the VCSEL/CMOS emitter and 500 MHz for each channel on photoreceiver were measured, respectively. We integrated the optical interconnects using free-space optical alignment and demonstrated serial and parallel transmissions of digital data and video images.
A free-space integrated optoelectronic interconnect was built to explore parallel data transmission and processing. This interconnect comprises an 8 X 8 substrate-emitting 980-nm InGaAs/GaAs quantum-well vertical-cavity surface- emitting laser (VCSEL) array and an 8 X 8 InGaAs/InP P-I- N photodetector array. Both VCSEL and detector arrays were flip-chip bonded onto the complimentary metal-oxide- semiconductor (CMOS) circuitry, packaged in pin-grid array packages, and mounted on customized printed circuit boards. Individual data rates as high as 1.2 Gb/s on the VCSEL/CMOS transmitter array were measured. After the optical alignment, we carried out serial and parallel transmissions of digital data and live video scenes through this interconnect between two computers. Images captured by CCD camera were digitized to 8-bit data signals and transferred in serial bit-stream through multiple channels in this parallel VCSEL-detector optical interconnect. A data processing algorithm of edge detection was attempted during the data transfer. Final images were reconstructed back from optically transmitted and processed digital data. Although the transmitter and detector offered much higher data rates, we found that the overall image transfer rate was limited by the CMOS receiver circuits. A new design for the receiver circuitry was accomplished and submitted for fabrication.
The presentation gives an overview of the ongoing Army Research Laboratory (ARL)/University of Maryland research effort on vertical-cavity-surface-emitting-laser (VCSEL) interconnects and OE processing and why this technology is of interest. ARL is conducting a research and development effort to develop VCSELs, VCSEL arrays, and their hybridization with complimentary metal-oxide-semiconductor (CMOS) electronics and microwave monolithic integrated circuits (MMICs). ARL is also very active in the design, modeling, and development of diffractive optical elements (DOEs). VCSEL-CMOS flip-chip optoelectronic circuits and DOEs are of interest together with detector-CMOS flip-chip circuits to provide digital and analog optoelectronic interconnects in optoelectronic processing architectures. Such optoelectronic architectures show promise of relieving some of the information flow bottlenecks that are emerging in conventional digital electronic processing as the electronic state of the art advances at a rapid pace and the electronic interconnects become a significant limitation. Such optoelectronic interconnects are also of interest in the development of analog optoelectronic processing architectures that are very difficult to implement in conventional electronic circuitry due to the incorporation of dense arrays of interconnects between electronic elements. VCSEL-MMIC- detector flip-chip circuits are of interest for the incorporation of optoelectronic interconnects into analog RF systems where the optoelectronic interconnect offers advantages of size, weight, bandwidth, and power consumption. VCSEL-MMIC interconnects may also play a role in future high- speed digital optoelectronic processing.
KEYWORDS: Vertical cavity surface emitting lasers, Sensors, Photodetectors, Signal detection, Optoelectronics, Optical interconnects, Modulation, Signal attenuation, Detector arrays, Chemical elements
We demonstrate an optoelectronic interconnect based on an 8 by 8 array of vertical-cavity surface-emitting lasers, an 8 by 8 array of photodetectors, and a single compound lens. The substrate-emitting VCSEL array and back-illuminated photodetector array were flip-chip bonded to a CMOS driver circuit and a Si fan-out pad array, respectively. The CMOS driver provides laser addressing, signal conditioning and modulation current.In this paper we will describe the interconnect configuration, device structures and characteristics, and CMOS driver circuits. We then discuss the system operation and performance.
KEYWORDS: Signal processing, Cameras, Signal detection, Clocks, Analog electronics, Adaptive optics, Image processing, Charge-coupled devices, CCD cameras, Radar signal processing
A 1D camera was developed to provide a small high-dynamic-range, high- resolution imager for use in a variety of optical processors. The camera is built around a high-performance 16-port 1024-pixel by 1-line charge- coupled device (CCD) array. The array and associated drive circuitry are integrated into a compact camera head. The camera contains a three-board set consisting of the array and its output buffers, a clock driver board, and a timing control board. Because of the parallel output structure, the readout time can be less than 10microsecond(s) , giving a maximum data output rate of over 100 million pixels per second. The camera has a dynamic range of over 55 dB of optical intensity. The camera electronically buffers the CCD outputs to drive 75-ohm coaxial cables to an external array of analog multiplexers and an analog to digital converter (ADC). At the highest transfer rate of over 100,000 lines per second, 16 ADCs could be used to read all the channels simultaneously. The camera also provides transistor-transistor logic (TTL) clocking waveforms, which are converted to metal oxide semiconductor (MOS) voltage levels to control and drive the CCD array. In order to allow a sufficient amount of flexibility, the camera provides different adjustable parameters and interface options for the user. Interface options include selection of an internal or external clock source, a shutter signal, and an internal/external trigger source.
A compact and fully integrated, high-frame-rate and high-resolution digital image acquisition and analysis system has been developed. The system integrates high-speed data acquisition, image playback, image processing, and motion analysis features. The imaging device, a multiport, split-frame-transfer, backside-illuminated charge-coupled device (CCD) imager developed by the Army Research Laboratory and the David Sarnoff Research Center, enables system operation at up to 500 frames per second. The system design is described and CCD performance results are given.
Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.
A second generation of high-frame-rate 512 X 512 and 1024 X 1024 pixel CCD imagers has been fabricated. These thinned, back-illuminated frame transfer imagers, designed for optical signal-processing applications, employ a split-frame transfer into dual storage registers and multiple output ports for increased frame rates. Reported here are measured characteristics of 16-port 512 X 512 and 32-port 1024 X 1024 imagers from the second design/fabrication cycle. Data are presented characterizing quantum efficiency, dynamic range, antiblooming control operation, high-speed performance, and on-chip correlated-double-sampling amplifier noise.
We describe the architecture of high-frame-rate, frame-interline-transfer CCD arrays designed for optical signal processing applications. A gain-compression scheme is implemented in the pixel structure to increase the optical detection dynamic range. Simulation results are presented and compared with test results of imagers from the first fabrication lot.
This paper reports recent progress by the authors in two distinct charge coupled device (CCD) technology areas. The first technology area is high frame rate, multi-port, frame transfer imagers. A 16-port, 512 X 512, split frame transfer imager and a 32-port, 1024 X 1024, split frame transfer imager are described. The thinned, backside illuminated devices feature on-chip correlated double sampling, buried blooming drains, and a room temperature dark current of less than 50 pA/cm2, without surface accumulation. The second technology area is vacuum ultraviolet (UV) frame transfer imagers. A developmental 1024 X 640 frame transfer imager with 20% quantum efficiency at 140 nm is described. The device is fabricated in a p-channel CCD process, thinned for backside illumination, and utilizes special packaging to achieve stable UV response.
A high frame rate visible CCD camera capable of operation up to 200 frames per second is described. The camera produces a 256 X 256 pixel image by using one quadrant of a 512 X 512 16-port, back illuminated CCD imager. Four contiguous outputs are digitally reformatted into a correct, 256 X 256 image. This paper details the architecture and timing used for the CCD drive circuits, analog processing, and the digital reformatter.
Peter Levine, Donald Sauer, Fu-Lung Hseuh, Frank Shallcross, Grazyna Meray, Gordon Taylor, Gary Hughes, John Pellegrino, Deborah Simon, Lorna Harrison, William Lawler
Back-illuminated, 16-port 512 X 512 and 32-port 1024 X 1024 charge coupled device (CCD) imagers have been fabricated. The measured performance of the 512 X 512 pixel chip is described, including data on quantum efficiency, dynamic range, dark current, frame rates, uniformity, contrast transfer function, and on-chip correlated double- sampling (CDS) amplifier noise. We have previously reported on these designs. The CCD arrays are designed with a unique combination of parameters optimized for applications requiring high resolution combined with high frame rates and wide dynamic range. The imaging registers achieve 100% optical fill factor and high quantum efficiency through the use of substrate thinning and back-side illumination. The high frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports which reduce the 512 X 512 array readout frequency to 15 MHz for 800 frame per second operation. On- chip CDS amplifiers are included in each output port to reduce the readout noise and simplify off-chip analog signal processing. Both designs include a buried anti-blooming drain structure and electro static discharge (ESD) protection.
A technique for real time direct measurement of both the amplitude and phase of photorefractive space charge fields during grating formation is presented. Photorefractive gratings are formed by the interference pattern of two intensity modulated beams. The two beams are single sideband modulated at the same RF frequency but are of opposite frequency shift. A detector tuned to the modulation frequency is used to monitor the time development of both the amplitude and phase of the photorefractive grating using a heterodyne detection scheme. This technique provides substantial dynamic range and the necessary sensitivity for the detection of refractive index changes as small as 10-8 and phase changes as small as 1 degree(s). Data is presented for the build-up of the amplitude and phase of the photorefractive space-charge fields. The photorefractive physical properties of these crystals including diffusion transport length, photovoltaic transport length, screening length, and the mobility free carrier lifetime product are determined.
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