As the demand for analog-to-digital (A/D) conversion with greater bandwidths increase, it is necessary to look at other alternatives to electronics for integrated circuit design. One such approach to utilize is a combination of optics and electronics, or opto-electronics, at all levels of the system hierarchy. A device that has these properties is the Self Electro-optic Effect Device (SEED), and combining this with oversampling techniques for data conversion can meet the demands for direct digitization of radio frequency (RF) signals. One form of A/D oversampling conversion method is Sigma-Delta modulation. A key element of this technique is the subtractor and in this paper we will discuss the implementation of a differential subtractor using SEEDs as part of a Sigma-Delta Modulator. This paper will detail simulation results based on experimental data to predict the behavior of two types of differential subtractors, one of which will be compared with experimental results.
In this article photonic implementations of two oversampled analog-to-digital converter architectures are discussed. The first, and simplest design is that of pulse-code-modulation. Simulations and an experiment are developed employing a Multiple-Quantum-Well p-i-n diode comparator. Agreement between simulation and experiment is demonstrated and the design is subsequently extended to a higher performance first order unipolar sigma-delta architecture. Results of the signal-to-noise ratio as a function of input amplitude are presented for an oversampling ratio of 100.
KEYWORDS: Modulators, Modulation, Analog electronics, Quantum wells, Signal to noise ratio, Absorption, Optoelectronics, Electro optics, Data conversion, Diodes
Oversampled analog-to-digital conversion architectures provide a trade-off between sampling speed for improved amplitude resolution without the need for complex analog circuits. One form of oversampled data conversion techniques is sigma-delta (ΣΔ) modulation, which takes advantage of high sampling rates. In this paper, a performance evaluation on ΣΔ modulators based on measured data of Self Electro-optic Effect Devices are presented and discussed. The data are used in evaluating the performance of the A/D converter using MATLAB simulations.
Differential architectures for both first order error diffusion and
also first order sigm-delta modulators are presented in this
paper. Techniques required to transform single-ended architectures to
differential architectures are discussed which are suitable for
implementation in both PIN and NIN SEED technologies. Descriptions of
common SEED circuit modules, together with SPICE behavioural
simulations are also presented. A feature of the architectures
presented is that they can be fully integrated into a single substrate
using MEMS technologies. This can be done by incorporating integrated
optical waveguides together with MMIC technology. The goal of this
work is a fully integrated differential optical oversampling modulator
with extremely high resolution and linearity.
KEYWORDS: Error analysis, Digital filtering, Finite impulse response filters, Transistors, Pulse shaping, Quantization, Signal processing, Digital signal processing, Multiplexers, Clocks
A cascadable 10GOPS transversal filter chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti- symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4 - 2 compressors to reduce the transistor count. The chip was fabricated in a 0.35 micrometer CMOS process, measures 3.1 X 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz (200 MSa/s throughput). An error table compensator system using a lookup table has been built using the transversal filter programmed as a wideband differentiator with some additional on chip circuits including delays and an adder. An external memory stores the error table. The error table technique is capable of providing between 7 to 15 dB improvement in the dynamic range of typical 100 Ms/s A/D converters. An application to pulse shaping of high chip rate spread spectrum signals is also discussed.
This paper describes the design of very high speed optoelectronic analog digital converter based on a digital division algorithm called SRT division using n-i(MQW)-n self electro-optic effect device (SEED) technology. The proposed structure is a pipeline ADC. The SRT algorithm was chosen because it provides a redundancy per stage of the pipeline. The amount of redundancy is dependent on the radix of the SRT algorithm and the number set chosen. The relation between the SRT radix, number set and the division full range is given in this paper. Also a macro-model for the n- i(MQW)-n device was developed and used to simulate all the circuitry and algorithmic operations needed for the ADC. These included analog addition, analog subtraction and integer multiplication. Based on the developed macro-model and n-i(MQW)-n SEED circuit modules a basic unit of the algorithm ADC was designed.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.