Silicon Ring Resonators (RR) are currently being assessed by several national metrology organizations as thermometers for use in calibration laboratories and in high-accuracy commercial applications. In this paper, we summarize the results of one such assessment carried out at the National Research Council of Canada (NRC). The prototype of silicon RR thermometer (developed at NRC) was evaluated in the stirred liquid bath between 23 °C and 80 °C over the period of several years in order to get the full uncertainty budget. The combined 10-mK standard uncertainty for our RR thermometer is not only identical to the repeatability reported previously for an unpackaged RR but it also includes a contribution due to long-term drift of RR thermometer estimated over two consecutive 11-month periods. We also report the results of our on-going efforts to reduce the long-term drift by using the controlled gas atmosphere inside RR thermometer and discuss the ultimate accuracy achievable with our current setup.
The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.
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