Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from
test result diagnostics. Product engineers will analyze the diagnostic results and perform a number
of physical failure analyses to detect systematic defects which cause yield loss for these sets of
wafers in order to feedback the information to process engineers for process improvements. Most
of time, the systematic defects that are detected are major issues or just one of the causes for the
overall yield loss.
This paper will present a working flow for using design analysis techniques combined with
diagnostic methods to systematically transform silicon testing information into physical layout
information. A new set of the testing results are received from a new lot of wafers for the same
product. We can then correlate all the diagnostic results from different periods of time to check
which blocks or nets have been highlighted or stop occurring on the failure reports in order to
monitor process changes which impact the yield. The design characteristic analysis flow is also
implemented to find 1) the block connections on a design that have failed electrical test or 2)
frequently used cells that been highlighted multiple times.
It is very well known that as technology nodes move to smaller sizes, the number of design rules
increases while design structures become more regular and the process manufacturing steps have
increased as well. Normal inspection tools can only monitor hard failures on a single layer. For
electrical failures that happen due to inter layers misalignments, we can only detect them through
testing.
This paper will present a working flow for using pattern analysis interlayer profiling techniques
to turn multiple layer physical info into group linked parameter values. Using this data analysis
flow combined with an electrical model allows us to find critical regions on a layout for yield
learning.
Systematic yield detractors are normally expected to be identified by ATPG test result diagnostics.
Different test patterns have been designed to test different functions. Test diagnostics can identify
failed functions so that product engineers, based on testing results, can narrow down which block
in the design performs this function. However, it is often hard to narrow down to a more specific
region in a product.
This paper will present a working flow for using design diffing techniques to extract layout
structures and perform a geometry analysis flow combined with testing results to find most
probable suspects that may cause noticeable yield loss.
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