Dr. Steve Ayres Profile

Dr. Steve Ayres

Senior Applications Engineer at Hitachi High-Tech America Inc

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Publications (2)

Proceedings Article | 14 April 2014 Paper

Plasma etched surface scanning inspection recipe creation based on bidirectional reflectance distribution function and polystyrene latex spheres

Tiffany Saldana, Steve McGarvey, Steve Ayres

Proceedings Volume 9050, 905038 (2014) https://doi.org/10.1117/12.2057401

KEYWORDS: Plasma, Signal to noise ratio, Latex, Silica, Plasma etching, Light scattering, Optical spheres, Inspection, Semiconducting wafers, Bidirectional reflectance transmission function

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The continual increasing demands upon Plasma Etching systems to self-clean and continue Plasma Etching with minimal downtime allows for the examination of SiCN, SiO2 and SiN defectivity based upon Surface Scanning Inspection Systems (SSIS) wafer scan results. Historically all Surface Scanning Inspection System wafer scanning recipes have been based upon Polystyrene Spheres wafer deposition for each film stack and the subsequent creation of light scattering sizing response curves. This paper explores the feasibility of the elimination of Polystyrene Latex Sphere (PSL) and/or process particle deposition on both filmed and bare Silicon wafers prior to Surface Scanning Inspection System recipe creation. The study will explore the theoretical maximal Surface Scanning Inspection System sensitivity based on PSL recipe creation in conjunction with the maximal sensitivity derived from Bidirectional Reflectance Distribution Function (BRDF) maximal sensitivity modeling recipe creation. The surface roughness (Root Mean Square) of plasma etched wafers varies dependent upon the process film stack. Decrease of the root mean square value of the wafer sample surface equates to higher surface scanning inspection system sensitivity. Maximal sensitivity SSIS scan results from bare and filmed wafers inspected with recipes created based upon Polystyrene/Particle Deposition and recipes created based upon BRDF modeling will be overlaid against each other to determine maximal sensitivity and capture rate for each type of recipe that was created with differing recipe creation modes. A statistically valid sample of defects from each Surface Scanning Inspection system recipe creation mode and each bare wafer/filmed substrate will be reviewed post SSIS System processing on a Defect Review Scanning Electron Microscope (DRSEM). Native defects, Polystyrene Latex Spheres will be collected from each statistically valid defect bin category/size. The data collected from the DRSEM will be utilized to determine the maximum sensitivity capture rate for each recipe creation mode. Emphasis will be placed upon the sizing accuracy of PSL versus BRDF modeling results based upon automated DRSEM defect sizing. An examination the scattering response for both Mie and Rayleigh will be explored in relationship to the reported sizing variance of the SSIS to make a determination of the absolute sizing accuracy of the recipes there were generated based upon BRDF modeling. This paper explores both the commercial and technical considerations of the elimination of PSL deposition as a precursor to SSIS recipe creation. Successful integration of BRDF modeling into the technical aspect of SSIS recipe creation process has the potential to dramatically reduce the recipe creation timeline and vetting period. Integration of BRDF modeling has the potential to greatly reduce the overhead operation costs for High Volume Manufacturing sites by eliminating the associated costs of third party PSL deposition.

Proceedings Article | 10 May 2005 Paper

Inline sidewall angle monitoring of memory capacitor profiles

Ben Rathsack, Scott Bushman, Francis Celii, Stephen Ayres, Roman Kris

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.600750

KEYWORDS: Capacitors, Etching, Scanning electron microscopy, Atomic force microscopy, Scatterometry, Composites, Metrology, 3D modeling, Semiconducting wafers, 3D metrology

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The integration of embedded ferroelectric random access memory (FRAM) into a standard CMOS flow requires significant control and characterization of the patterned capacitor sidewall angle. The electrical functionality of the FRAM capacitor is highly dependent on the post-etch sidewall characteristics of the TiAlN hardmask and Ir/PZT/Ir capacitor film stack. In this study, we explored various options for determining the sidewall profile of these capacitors including scanning electron microscope (SEM), atomic force microscopy (AFM) and scatterometry. A series of capacitor samples with ranges of sidewall slopes from 60 degrees to 80 degrees was generated to test each measuring technique's robustness. All of the techniques demonstrated relatively accurate sidewall angle measurements of the high-angle capacitor profiles relative to cross-section SEMs. However, the CD SEM had difficulty identifying the top edge of the low-angle capacitor samples due to the large amount of profile roughness, which induced a large measurement error range. Additional optimization is required to improve the CD SEM's precision, before it would be a viable in-line monitor for the FRAM process. The AFM provided good accuracy and precision on the high-angle capacitor profiles, but the tip size limited the measurements to spaces larger than 120 nm. Furthermore, the AFM had a long move-acquire-measure (MAM) time of 5 minutes/site, which limited its throughput as an inline monitor. The scatterometer predicted bottom-stack sidewall angle measurements (2 trapezoid model) that were consistent with the cross-section SEMs, and it produced the lowest across wafer sidewall angle range. It also had the fastest MAM time of 5 seconds/site compared to the other techniques. However, it was difficult to generate an accurate scatterometry model due to the complex optical film stack that incorporated low surface reflectivity and higher surface roughness. While each technique had limitations, scatterometry appeared to be the most capable of inline sidewall angle monitoring.

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